Python-Verilog (Pyverilog)

[Bobby]

I am working on my own domain-specific language (DSL). The DSL is based on functional requirements of a device under test (DUT). The grammar has rules like 'if' and 'else'. I have made a grammar of my DSL without any programming code in my grammar. I am using ANTLR to generate Parser, Lexer, Visitor and Listeners in Python. I have made the visitor pattern in python to parse the input I give to my grammar. The input I am parsing is in natural words as my grammar itself consists of natural words rules. Therefore the input is not a programming language. Now I have a working visitor in python which can successfully interpret my input.
 
I would like to generate a Verilog test bench structure from this stage on wards. Literally blocked at this point. I have come across this toolkit Pyverilog. It has a Verilog code generator as a tool. In this Verilog code generator, a Verilog HDL code is represented by using the AST classes defined in its parser called'vparser.ast'.

Can I use this code generator as a standalone for my Python visitor pattern which I have made from my ANTLR ? Any workaround that I can use this kit considering the above mentioned scenario ?

I would appreciate any suggestion.