SAGE for FPGA development

[Stef Mientki]

Blubaugh, David A. wrote:
>  because labview is neither free nor open source.  Labview is not the
> route to go for someone like me who has no real capital.  
>
>   
I thought you were doing your master thesis ?
And LabView is almost for free, for people linked in anyway to an 
educational institute !

But to be honest, I don't like LabView very much and would love to see 
an open source alternative !

succes,
cheers,
Stef Mientki
> David Blubaugh
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> -----Original Message-----
> From: Stef Mientki [mailto:stef.mientki at gmail.com] 
> Sent: Thursday, February 14, 2008 1:25 PM
> To: python-list at python.org
> Subject: Re: SAGE for FPGA development
>
> Blubaugh, David A. wrote:
>   
>> Bill,
>>
>>
>> Let me first say that my FPGA experiences are of the following nature:
>>
>> 1.) Developed control algorithms onto a FPGA that were utilized to
>> control a switch-reluctance motor (three-phase as well six-phase).  
>>
>> 2.) I am currently in the process of developing a specialized
>> Multidimensional FFT processor that can be utilized to determine the
>> frequency content and angle of arrival of a target via a linear sensor
>> array.  
>>
>> I believe that you are deeply mistaken about that I would be the only
>> person to use such a system.  The FPGA market will only increase as
>>     
> more
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>> embedded systems utilize more and more FPGAs for the processing needs,
>> since embedded system are being task with more computationally
>>     
> intensive
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>> tasks, such as for example, image digital signal processing within
>> portable digital cameras.  Electrical and Computer Engineers could
>>     
> start
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>> to utilize SAGE for system programming and development, not just only
>> mathematicians or physicists doing their own selected work.
>>
>> Also, I think that you may have the wrong idea of porting SAGE to be
>> executed within a FPGA.  What I had in mind was to have MyHDL embedded
>> within SAGE, where sage could handle the graphical plot outputs of
>>     
> what
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>> is being generated by MyHDL.  To be absolutely clear, SAGE could be
>>     
> used
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>> to handle the graphs for the simulation side of what the logic that is
>> being generated by MyHDL embedded within the SAGE framework.  This
>>     
> could
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>> help in testing algorithms as they are being generated into verilog
>>     
> FPGA
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>> logic, by having a graphical experience within the entire development
>> process.
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>> If you have any more additional questions, please contact me as soon
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>> possible.  
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> Why not use LabView, it seems to have good FPGA support ?
> cheers,
> Stef
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