MyHDL project!
Blubaugh, David A.
dblubaugh at belcan.com
Fri Feb 8 15:03:00 EST 2008
________________________________
From: Dan Fabrizio [mailto:dfabrizio51 at gmail.com]
Sent: Friday, February 08, 2008 2:56 PM
To: Blubaugh, David A.
Subject: Re: MyHDL project !!!!!
David,
No problem with the mailing list, others might have some experience that
could be useful. Let me know how you make out this weekend, I will be
doing the same on my end. FYI, I'm workin on an iMac.
Dan
On Feb 8, 2008 2:25 PM, Blubaugh, David A. <dblubaugh at belcan.com> wrote:
Hi Dan,
I think that is a great idea. However, I have done additional
reading and it appears that SAGE is really nothing more than python wrap
with scipy and laplack. Therefore, I think we can start on the same
thing together, since there is little reason to start a divergence
already in this project. I will try to integrate python with scipy and
MyHDL this weekend and I be giving you updates during the weekend. I
will try and see what I can get at this time. Also, do you have any
objections to me forwarding this message to the python community mailing
list?? thanks for being a friend.
Thanks,
David Blubaugh
Also, before I forget to mention. I am currently residing in
Springboro, Ohio, which is not far from Wright-Patterson Air Force Base.
________________________________
From: Dan Fabrizio [mailto:dfabrizio51 at gmail.com]
Sent: Friday, February 08, 2008 1:16 PM
To: Blubaugh, David A.
Subject: Re: MyHDL project !!!!!
Hi David,
No need to apologize. Reply when you get a chance, I realize
we all have other things we need to do like work and errands and family
and home projects, etc... I don't know at this point which one would
be better but let's evaluate both and try to select the best for our
needs. How about if you look at Sage and I look at SciPy, maybe we do a
simple DSP algorithm ( FIR filter ) in both if needed? What do you
think? We could do a floating point version, then follow up with a
fixed point version and then compare notes. Just some of my thoughts,
what are yours?
I live in USA on the east coast very close to Philadelphia, Pa.
How about you, where do you live?
I have strong interest in the development EDA CAD tools like
MyHDL. Most of my work recently has been in ASIC and FPGA design for
distributed digital audio and wireless communications products. I have
been working
on a Timing Analyzer program for a few years. It is about 75%
complete but is taking longer than expected being a part time effort. I
used Java and didn't know about Python when I started. Tcl/Tk is very
popular in a lot of CAD tools I use but it looks like Python is starting
to become popular as well. I have thought about converting the
application to Python but haven't decided for sure yet.
Regards,
Dan
On Feb 8, 2008 12:33 PM, Blubaugh, David A.
<dblubaugh at belcan.com> wrote:
Dan,
Let first apologize for not answering your message
sooner. I was currently experiencing car problems and was extremely
late to work. I arrived at work almost at 12:00. My reason for
selecting the SAGE environment, is that the SAGE environment appears to
be a far more mature environment than SciPy/NumPy/Matplotlib
combination. I thought that using SAGE could be able to develop better
results sooner than the other combination. However, the most important
thing to keep in mind for any endeavor is that we MUST keep everything
involved as simple as possible. Which do you believe would be easier to
develop and use SAGE or a SciPy/NumPy/Matplotlib combination??? Thanks
for all of your sincere help and consideration.
David
________________________________
From: Dan Fabrizio [mailto:dfabrizio51 at gmail.com]
Sent: Thursday, February 07, 2008 7:59 PM
To: Blubaugh, David A.
Subject: Re: MyHDL project !!!!!
Hi David,
Your welcome. I am glad to have found a new friend as
well and yes, I am interested in helping you on
this project.
I have a question, why have you decided to use sage and
not SciPy/NumPy/Matplotlib combination?
Dan
On Feb 7, 2008 5:51 PM, Blubaugh, David A.
<dblubaugh at belcan.com> wrote:
Hello Dan,
Thank you very much for your reply. Yes, I am
planning to go to final FPGA implementation. Do not worry about the
master's thesis. I would not give such a curse such as that. I would
like to work on much smaller projects, which could then be latter on
combined to form into much larger projects. I have just e-mailed the
inventor of SAGE, which is a python implementation of MATLAB-like
environment. Would you like to work on the integration of MyHDL into
SAGE as a place to start?? Thanks for being a new friend.
David
________________________________
From: Dan Fabrizio
[mailto:dfabrizio51 at gmail.com]
Sent: Thursday, February 07, 2008 5:42 PM
To: Blubaugh, David A.
Subject: Re: MyHDL project !!!!!
Hi David,
I have been thinking about your project and feel
it is to much to take on at this time for me. I would be
happy to discuss ideas with you along the way if
needed. I was thinking that you have write floating point
Python for the algorithms first and analyze
results. If satisfied, then convert the floating point to MyHDL
fixed point algorithms that can be translated to
Verilog. Simulate the verilog rtl and verify the results. Are
you going to an FPGA?
Dan
On Feb 6, 2008 3:24 PM, Blubaugh, David A.
<dblubaugh at belcan.com> wrote:
Sir,
It has been quite some time since your
last message. Are you still interested in this project???
David
________________________________
From: Dan Fabrizio
[mailto:dfabrizio51 at gmail.com]
Sent: Friday, February 01, 2008 11:14 AM
To: Blubaugh, David A.
Subject: Re: MyHDL project !!!!!
David,
Let's start by discussing your masters
thesis subject in more detail.
We can take a project from conception to
hardware using MyHDL, NumPy
and SciPy. Maybe you could use this
project as a proof for your
thesis showing this methodology warrants
consideration compared other
ASIC/FPGA flows.
Let's discuss some of your ideas and
decide how to proceed.
Dan
On Feb 1, 2008 10:43 AM, Blubaugh, David
A. <dblubaugh at belcan.com> wrote:
Dan,
I would be honored to start a project
such as that in mind. How do we
begin ??????
David Blubaugh
-----Original Message-----
From: chewie54
[mailto:dfabrizio51 at gmail.com]
Sent: Thursday, January 31, 2008 9:34 PM
To: python-list at python.org
Subject: Re: Will Python on day
replaceMATLAB?????????????????????????????????????????????????????
> I have been evaluating the python
environment ever more closer. I
> believe I can interface python with a
development environment known as
> the ImpulseC environment. The
ImpulseC environment develops C to VHDL
> for FPGA development. I would
especially love to interface Python
> with ImpulseC and the graphing
capabilities of GNU Plot and SciPy in
> order to recreate a VHDL development
environment that will be just as
> capable as a $50,000 dollar Matlab to
VHDL toolbox. This is also a
> part of my Masters thesis. Is anyone
willing to help in this
endeavor?????
>
> David Blubaugh
>
Why not use MyHDL which is written in
Python and translates to Verilog.
I assume ImpulseC is a commercial
product and costs a log. MyHDL is
free.
If you have any interests in combining
MyHDL with SciPy and NumPy I
would be interested in getting involved.
Dan Fabrizio
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