Exploiting Dual Core's with Py_NewInterpreter's separated GIL ?

[Ross Ridge]

Paul Rubin wrote:
> I dunno about x86 hardware signals but these instructions do
> read-modify-write operaitons.  That means there has to be enough
> interlocking to prevent two cpu's from updating the same memory
> location simultaneously, which means the CPU's have to communicate.
> See <http://en.wikipedia.org/wiki/MESI_protocol> (I think this is
> how the current x86's do it):

The MESI protocol is used to ensure all read and write operations are
cache coherent, not just locked read-modify-write operations.  Whether
the LOCK prefix is used or not in an instruction normally isn't
externally visable.  From IA-32 Intel® Architecture Software
Developer's Manual Volume 3A: System Programming Guide, Part 1:

    For the Pentium 4, Intel Xeon, and P6 family processors,
    if the area of memory being locked during a LOCK operation
    is cached in the processor that is performing the LOCK operation
    as write-back memory and is completely contained in a cache line,
    the processor may not assert the LOCK# signal on the bus. Instead,
    it will modify the memory location internally and allow it's
    cache coherency mechanism to insure that the operation is carried
    out atomically. This operation is called "cache locking."
    The cache coherency mechanism automatically prevents two or
    more processors that have cached the same area of memory from
    simultaneously modifying data in that area.

The cost of mantaining cache coherency for a locked increment
instruction should be no different than that of an unlocked increment
instruction.

                                             Ross Ridge