[ANNOUNCE] MyHDL 0.5 released

[Jan Decaluwe]

Michael wrote:

> Practical examples are great, I'd seen that you'd introduced conversion to
> verilog some time back, but it wasn't clear how much was synthesisable.

I'll try to clarify. Hardware synthesis is a rather "closed" technology,
with several competing, expensive tools and relatively few practicers.
Hopefully this will change, e.g. with development tools like Xilinx ISE.
Mainstream synthesis starts from the RTL (register transfer) level and
is somewhat limited. So you have to learn about its constraints to write
synthesizable code. These are largely independent of the HDL you use.

The primary (and advertized) goal of MyHDL conversion to Verilog is
implementation through synthesis. However, succesful conversion
doesn't provide any guarantee on synthesizability. Indeed, the
convertor's constraints are much less severe than synthesis constraints:
they are defined mainly by restrictions of the target language. For
example, the convertor can convert while loops, even though they are not 
(RTL) synthesizable.

In fact I try to keep the convertor as general as possible, so that
it is also possible to convert higher-level code such as test
benches. I may need this as a substitute for co-simulation once
I tackle conversion to VHDL later this year.

In summary, when using MyHDL you still have to learn about synthesis,
just like in Verilog or VHDL.

> I've had some limited experience with
> compilation to hardware in the past, specifically to asynchronous hardware,
> but given you write code that can include loops, conditionals and these can
> be translated to FPGA descriptions and then run this for me blurs the
> hardware/software distinction. A specific example that looks like software
> I'm thinking of is this:
>    http://www.cs.man.ac.uk/fmethods/projects/AHV-PROJECT/node8.html

For examples such as this, you may have to scale down expectations. If
a loop defines behavior that spans multiple clock cycles, you'll have
to describe it as a finite state machine to make it (RTL) synthesizable.

> Maybe I should continue this conversation on the MyHDL list, since I'd be
> interested in getting started in this in a simple way.

You're welcome!

Jan

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