MyHDL 0.5 released

[Jan Decaluwe]

Randall Parker wrote:
> Jan,
> 
> What do you see as the main advantage for using MyHDL rather than VHDL
> for coding up a chip design?

The fact that MyHDL is technically just another Python application.

So it makes all typical Python advantages available to hardware
designers. No need to discuss those in this forum :-). An additional
advantage for this case may be that Python is a "mainstream"
language, while VHDL/Verilog are really niche languages.

Those who agree with the above may still have two questions:
1) is it meaningful?
2) can it be done?

I believe it's meaningful because in my view digital hardware
design can be regarded as just another specialized software
engineering discipline. Of course, things have to be learned,
but it's not more difficult than other application domains.
I should add that this is not the mainstream view of the
hardware design community :-)

I also believe that MyHDL convincingly shows that it can
be done: in other words, that it has all features of a
true HDL. Technically, the principal idea is the use Python
generators to model concurrency. Actually, I have also
tried hard to make it a *better* HDL, and I believe it is :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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