ANNOUNCE: MyHDL 0.4
Jan Decaluwe
jan at jandecaluwe.com
Thu Feb 5 12:14:59 EST 2004
I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
package for using Python as a hardware description & verification
language.
MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code. This feature provides a direct path
from Python to an FPGA or ASIC implementation.
For the details on the release, go here:
http://jandecaluwe.com/Tools/MyHDL/whatsnew04/whatsnew04.html
For a general overview and starting point, go here:
http://jandecaluwe.com/Tools/MyHDL/Overview.html
Regards, Jan
--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Python is fun, and now you can design hardware with it:
http://jandecaluwe.com/Tools/MyHDL/Overview.html
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