Writing Hardware Simulators?

[Jan Decaluwe]

Miki Tebeka wrote:
> Hello Donald,
> 
> 
>>I take it that this is an instruction set simulator (ISS) rather than an 
>>RTL level simulator?
> 
> Not so sure about the difference (RTL = Real Time Logic?).
> It should simulate the CPU and some peripherials as well.
> Currently I can ignore the pipline and some other stuff.

RTL = Register Transfer Level. This is a hardware description style
that models transfers between registers. In practice, it is often
used to refer to "synthesizable" hardware models, that is, models
that can be converted to a gate implementation automatically.

If you need to model hardware, it may be easier when you have a
light-weight model for deterministic concurrency. This is what
so-called "hardware description languages" (HDLs) provide. I wrote
a package that turns Python into an HDL, using generators:

    http://jandecaluwe.com/Tools/MyHDL/Overview.html

There is a one-week old mailing list:

    http://sourceforge.net/mail/?group_id=91207

with a nntp gateway though gmane:

    nntp://news.gmane.org/gmane.comp.python.myhdl

Nick Patavalis has just posted an example CPU simulator
to this mailing list, so you may want to check it out.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
    Bored with EDA the way it is? Check this:
    http://jandecaluwe.com/Tools/MyHDL/Overview.html