Metasyntax/Macros

[Paddy McCarthy]

"Terry Reedy" <tjreedy at udel.edu> wrote in message news:<iUudnYfQA-6tHV-jXTWcqw at comcast.com>...
> "Paddy McCarthy" <paddy3118 at netscape.net> wrote in message
> news:2ae25c6b.0305140003.dbd812e at posting.google.com...
> > I went googling for messages on Python and adding a macro facility,
> > but ended up with just too many hits and got lost.
> >
> > The reason I was looking was that I can get envisage an application
> > but seemed to remember that the addition of macros to Python got
>  shot
> > down before but could not remember the reasons.
> 
> They are all in the hits you gave up on ;-)  (Try just those in 2002.)
> One quick summary is that Guido wants Python code to look like Python
> code and be more or less universally readable by other Python
> programmers.  He is not going to be the one to help fork Python into
> separate sublanguage communities.
> 
Ahh, are you saying then that with other languages that have such a
facility, there is a lot of support for syntax generated by sets of
macros?

I would of thought that language designers/developers would support
the correct implimentation of the macro facility, and that support for
a particular macro set would be like support for Python programs now.

> > specific languages such as Specman and Vera. If Python was that
>  higher
> > level language then i thought that a macro facility would allow some
> > of the domain specific languages syntax to be re-used , People could
> > write
> >
> >  module my_mod (x,y,z) ...
> >
> > and create a Python class.
> 
> This shows the problem already.  'Module' is already in use to refer
> to modules, which are different from classes.  If a person has such a
> misunderstanding, what will they make of sys.modules?  -- or of the
> word 'module' in all current Python
> writings.
I guess my example was too simple.
If I wrote a library to support testing Verilog code, then the Verilog
programmers have a way representing concepts that may have ( an
extended ), representation in the Python library. I thought that a
Python macro facility might allow the library developer to also supply
macros that helped the Verilog 'bridge the gap' between Verilog and
the Python library.

Such code may be less readable to the 'out=of-domain' Pythoneer, but
*should* be more readable to the Verilog programmer, (or it's of no
use).

Please also remember my idea that the macro feature set should be able
to both expand macros to 'pristine' Python, and also to take Python
source and macro definitions and automatically generate 'coloured'
Python were macros have been applied whenever possible.
> 
> You can, of course, use the C preprocessor or equivalent to make such
> word-to-work translations before feeding the result to a Python
> interpreter.

I wouldn't want a file to file preprocessor as I have a gut feeling
that macros as part of the interpreter would be much more powerful - I
just don't know in what ways. (Meta-macros anyone :-)

> 
> Terry J. Reedy

Thanks for helping me explore the idea.

Donald 'Paddy' McCarthy.