ANNOUNCE: MyHDL 0.1 (also RHDL)

[Phil Tomson]

I'd like to also mention that I wrote a package called RHDL (Ruby Hardware 
Description Language - an HDL based on Ruby (http://www.ruby-lang.org)) 
about a year ago.  I really need to work on some 
docs for it ;-)  It has similar goals to MyHDL, but RHDL looks a lot more 
like VHDL.  Here's an example of a counter in RHDL ('#'=comment):


class My_Counter < RHDL::Design
  include RHDL #mixin RHDL methods
  def initialize(rst,clk,counter)
    inputs  = { 'RST' => Port.new(rst),
		'CLK' => Port.new(clk)}
    outputs = { 
		'COUNTER' => Port.new(counter)
	      }
    super(inputs,outputs)
    #define internal signals

    clk_events = 0
    define_behavior { 
	              process(counter){
			puts "-->Start of First Process"
			wait { clk_events == 3 }
		        puts "counter = #{counter}"
			puts "<--End of First Process"
		      }
		      process(clk) {
			puts "--->Start of Second Process"
			#synchronous reset
			if clk == '1' && clk.event 
			  if rst == '1'
			    counter.assign 0
			  else
		            counter.assign(counter + 1)
			  end
			  clk_events += 1
			end
			puts "clk_events = #{clk_events}"
			puts "<---End of Second Process"
	    	      }
  }
  end
end

My_Counter is a class so it can be instantiated as follows:

      rst = Signal.new(Bit.new('0'))
      clk = Signal.new(Bit.new('0'))
      count = Signal.new(0)
      mc = My_Counter.new(rst,clk,count)


RHDL allows concurrent processes including wait statements.  You can code 
at a structural or behavioral level and hierarchy is supported.

I haven't worked on it for a few months, but I do plan to keep developing 
it.  You'll notice that it looks a lot like VHDL.  One idea would be to 
allow it to look like either VHDL or Verilog by mixing-in (the 'include' 
above) a different module.  So, for example, if you mixed in a module 
called RHDL::Verilog you could use 'always' instead of 'process'.
In the short term I really do need to work on the docs and web 
page(MyHDL's docs are quite nice).

In article <3E6DAE83.C036107F at jandecaluwe.com>,
Jan Decaluwe  <jan at jandecaluwe.com> wrote:
>Thomas Heller wrote:
>> 
>> Jan Decaluwe <jan at jandecaluwe.com> writes:
>> 
>> > I am happy to announce the initial public release of MyHDL, a Python
>> > package for using Python as a hardware description language.
>> >
>> > This may be of interest to:
>> > - Pythoneers interested in applications of Python generators
>> > - hardware designers interested in the wonders of Python
>> 
>> Or Python programmers also doing VHDL from time to time...
>> 
>>
>> >
>> 
>> What will be the future of this package?  
>
>I will be actively promoting/developing it in the short term, but
>in the longer term this will depend on the amount of user interest.
>A good sign would be if people start complaining about performance,
>because that would mean they are actually using it <wink>.  (The bad
>news would be that someone, perhaps me, would then have to recode 
>the package as an extension module in C.)
>
>First on my list is to couple the package to a HDL simulator. My
>goal is to be able to use Python's unit test framework on hardware
>design written in an HDL - I believe Python would make a superior HVL.

I've got the same idea for RHDL - Ruby has a very nice unit testing 
framework and I use it to test RHDL.

>Unfortunately, I don't have access to any commercial simulator right
>now - only Icarus Verilog and I'm not sure that it supports the
>Verilog PLI completely. 

Same here.  But Icarus is a good start.  BTW: Is there any way to do this 
sort of thing with a VHDL simulator?  I would tend to think not.

>I'm also not yet clear on how to do it best -
>probably the best is to run MyHDL code in slave mode without
>time queue (delta cycles only)

>
>>Ideas I have for it include
>> generation of VCD files to view the simulation results in graphical
>> mode, 
>
>Definitely possible and interesting of course, but don't count on me for 
>that one. 
>
>>and (eventually) generating VHDL code.
>
>Well anticipated - it should indeed possible to generate HDL code from
>an elaborated MyHDL description - this could be interesting for the 
>synthesizable subset for example. I guess I would tackle Verilog
>first - as a back-end format it is just fine <wink>.
>

How would you go about doing this?  Would you get a parse tree of the 
Python program and then work with that?  I've been thinking of doing this 
with RHDL as well - I could get a parse tree of the Ruby code (from Ruby) 
and then walk the tree to generate code (or eventually, to do synthesis).


Phil