Turing Compliant?

[Will Ware]

Phil Hunt (philh at vision25.demon.co.uk) wrote:
: ... Python should output the 
: design of a special-purpose chip to solve the problem :-)

I remember reading a web page by a guy who wrote a chip in Scheme
and simulated it, and when the design and simulation were all done,
the program cranked out either VHDL or Verilog.
Maybe 1.6 should have a VHDLgen module. It would probably be
better if it worked from parse trees rather than bytecodes. More
opportunities for parallelism and other such optimizations.
Now that FPGA place&route software is willing to accept VHDL input,
maybe there should be a standard PCI-bus Python accelerator board.
-- 
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Resistance is futile. Capacitance is efficacious.
Will Ware	email:    wware @ world.std.com