[pypy-commit] pypy arm64: basic IMM support in add

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96217:13d01ec04e4e
Date: 2019-03-06 14:31 +0000
http://bitbucket.org/pypy/pypy/changeset/13d01ec04e4e/

Log:	basic IMM support in add

diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -23,9 +23,9 @@
         else:
             s = 0
         if l0.is_imm():
-            self.mc.ADD_ri(res.value, l1.value, imm=l0.value, s=s)
+            self.mc.ADD_ri(res.value, l1.value, l0.value)
         elif l1.is_imm():
-            self.mc.ADD_ri(res.value, l0.value, imm=l1.value, s=s)
+            self.mc.ADD_ri(res.value, l0.value, l1.value)
         else:
             self.mc.ADD_rr(res.value, l0.value, l1.value)
 
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -148,6 +148,22 @@
                 continue
             return free_regs[i]
 
+DEFAULT_IMM_SIZE = 4096
+
+def check_imm_arg(arg, size=DEFAULT_IMM_SIZE, allow_zero=True):
+    i = arg
+    if allow_zero:
+        lower_bound = i >= 0
+    else:
+        lower_bound = i > 0
+    return i <= size and lower_bound
+
+def check_imm_box(arg, size=DEFAULT_IMM_SIZE, allow_zero=True):
+    if isinstance(arg, ConstInt):
+        return check_imm_arg(arg.getint(), size, allow_zero)
+    return False
+
+
 class Regalloc(BaseRegalloc):
 
     def __init__(self, assembler):
@@ -280,16 +296,24 @@
         return [base_loc, value_loc]
 
     def prepare_op_int_add(self, op):
-        arg0 = op.getarg(0)
-        arg1 = op.getarg(1)
+        boxes = op.getarglist()
+        a0, a1 = boxes
         # XXX support immediates
-        l0 = self.make_sure_var_in_reg(arg0, op.getarglist())
-        l1 = self.make_sure_var_in_reg(arg1, op.getarglist())
+        imm_a0 = check_imm_box(a0)
+        imm_a1 = check_imm_box(a1)
+        if not imm_a0 and imm_a1:
+            l0 = self.make_sure_var_in_reg(a0, boxes)
+            l1 = self.convert_to_imm(a1)
+        elif imm_a0 and not imm_a1:
+            l0 = self.convert_to_imm(a0)
+            l1 = self.make_sure_var_in_reg(a1, boxes)
+        else:
+            l0 = self.make_sure_var_in_reg(a0, boxes)
+            l1 = self.make_sure_var_in_reg(a1, boxes)
         self.possibly_free_vars_for_op(op)
         res = self.force_allocate_reg(op)
         return [l0, l1, res]
 
-
     def prepare_int_cmp(self, op, res_in_cc):
         boxes = op.getarglist()
         arg0, arg1 = boxes
diff --git a/rpython/jit/backend/aarch64/test/test_instr_builder.py b/rpython/jit/backend/aarch64/test/test_instr_builder.py
--- a/rpython/jit/backend/aarch64/test/test_instr_builder.py
+++ b/rpython/jit/backend/aarch64/test/test_instr_builder.py
@@ -130,6 +130,15 @@
     @settings(max_examples=20)
     @given(rd=st.sampled_from(r.registers),
            rn=st.sampled_from(r.registers),
+           imm=st.integers(min_value=0, max_value=(1<<12)-1))
+    def test_ADD_ri(self, rd, rn, imm):
+        cb = CodeBuilder()
+        cb.ADD_ri(rd.value, rn.value, imm)
+        assert cb.hexdump() == assemble("ADD %r, %r, %d" % (rd, rn, imm))
+
+    @settings(max_examples=20)
+    @given(rd=st.sampled_from(r.registers),
+           rn=st.sampled_from(r.registers),
            ofs=st.integers(min_value=0, max_value=4095))
     def test_SUB_ri(self, rd, rn, ofs):
         cb = CodeBuilder()