[pypy-commit] pypy arm64: missing bits

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96878:d12d1f105c66
Date: 2019-06-27 17:36 +0000
http://bitbucket.org/pypy/pypy/changeset/d12d1f105c66/

Log:	missing bits

diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -354,7 +354,7 @@
             for i in range(0, len(r.caller_resp), 2):
                 mc.STP_rri(r.caller_resp[i].value, r.caller_resp[i + 1].value, r.sp.value, i * WORD)
             cur_stack = len(r.caller_resp)
-            mc.STP_rri(exc0.value, exc1.value, cur_stack * WORD)
+            mc.STP_rri(exc0.value, exc1.value, r.sp.value, cur_stack * WORD)
             cur_stack += 2
             for i in range(len(r.caller_vfp_resp)):
                 mc.STR_di(r.caller_vfp_resp[i].value, r.sp.value, cur_stack * WORD)
@@ -373,7 +373,7 @@
             for i in range(0, len(r.caller_resp), 2):
                 mc.LDP_rri(r.caller_resp[i].value, r.caller_resp[i + 1].value, r.sp.value, i * WORD)
             cur_stack = len(r.caller_resp)
-            mc.LDP_rri(exc0.value, exc1.value, cur_stack * WORD)
+            mc.LDP_rri(exc0.value, exc1.value, r.sp.value, cur_stack * WORD)
             cur_stack += 2
             for i in range(len(r.caller_vfp_resp)):
                 mc.LDR_di(r.caller_vfp_resp[i].value, r.sp.value, cur_stack * WORD)
@@ -462,6 +462,12 @@
         mc.RET_r(r.lr.value)
         self._frame_realloc_slowpath = mc.materialize(self.cpu, [])        
 
+    def _load_shadowstack_top(self, mc, reg, gcrootmap):
+        rst = gcrootmap.get_root_stack_top_addr()
+        mc.gen_load_int(reg.value, rst)
+        self.load_reg(mc, reg, reg)
+        return rst
+
     def _store_and_reset_exception(self, mc, excvalloc=None, exctploc=None,
                                    on_frame=False):
         """ Resest the exception. If excvalloc is None, then store it on the