[pypy-commit] pypy arm64: more float ops

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96823:8e29d4e40226
Date: 2019-06-18 15:13 +0000
http://bitbucket.org/pypy/pypy/changeset/8e29d4e40226/

Log:	more float ops

diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -890,9 +890,15 @@
         elif loc.is_stack():
             self.mc.LDR_ri(r.ip0.value, r.fp.value, loc.value)
             self.mc.STR_ri(r.ip0.value, r.sp.value, pos)
+        elif loc.is_vfp_reg():
+            xxx
         else:
             assert False, "wrong loc"
 
+    def _mov_imm_float_to_loc(self, prev_loc, loc):
+        assert loc.is_vfp_reg()
+        self.load(loc, prev_loc)
+
     def regalloc_mov(self, prev_loc, loc):
         """Moves a value from a previous location to some other location"""
         if prev_loc.is_imm():
diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -343,6 +343,13 @@
         assert base_loc.is_core_reg()
         if scale == 3:
             # WORD size
+            if value_loc.is_float():
+                if ofs_loc.is_imm():
+                    self.mc.STR_di(value_loc.value, base_loc.value,
+                                    ofs_loc.value)
+                else:
+                    xxx
+                return
             if ofs_loc.is_imm():
                 self.mc.STR_ri(value_loc.value, base_loc.value,
                                 ofs_loc.value)
@@ -365,6 +372,12 @@
         #
         if scale == 3:
             # WORD
+            if res_loc.is_float():
+                if ofs_loc.is_imm():
+                    self.mc.LDR_di(res_loc.value, base_loc.value, ofs_loc.value)
+                else:
+                    self.mc.LDR_dr(res_loc.value, base_loc.value, ofs_loc.value)
+                return
             if ofs_loc.is_imm():
                 self.mc.LDR_ri(res_loc.value, base_loc.value, ofs_loc.value)
             else:
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -97,6 +97,9 @@
         rffi.cast(rffi.CArrayPtr(longlong.FLOATSTORAGE), adr)[0] = x
         return locations.ConstFloatLoc(adr)
 
+    def call_result_location(self, v):
+        return r.d0
+
     def __init__(self, longevity, frame_manager=None, assembler=None):
         RegisterManager.__init__(self, longevity, frame_manager, assembler)
 
diff --git a/rpython/jit/backend/aarch64/registers.py b/rpython/jit/backend/aarch64/registers.py
--- a/rpython/jit/backend/aarch64/registers.py
+++ b/rpython/jit/backend/aarch64/registers.py
@@ -23,6 +23,9 @@
 
 callee_saved_registers = [] # x19, x20, x21, x22]
 vfp_argument_regs = caller_vfp_resp = all_vfp_regs[:8]
+[d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14,
+ d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27,
+ d28, d29, d30, d31] = vfpregisters
 
 argument_regs = [x0, x1, x2, x3, x4, x5, x6, x7]
 caller_resp = argument_regs + [x8, x9, x10, x11, x12, x13, x14, x15]