[pypy-commit] pypy arm64: enough for basic float operations
fijal
pypy.commits at gmail.com
Tue Jun 18 09:35:06 EDT 2019
Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96820:254778fcde03
Date: 2019-06-18 13:34 +0000
http://bitbucket.org/pypy/pypy/changeset/254778fcde03/
Log: enough for basic float operations
diff --git a/rpython/jit/backend/aarch64/arch.py b/rpython/jit/backend/aarch64/arch.py
--- a/rpython/jit/backend/aarch64/arch.py
+++ b/rpython/jit/backend/aarch64/arch.py
@@ -8,5 +8,5 @@
# A jitframe is a jit.backend.llsupport.llmodel.jitframe.JITFRAME
# Stack frame fixed area
# Currently only the force_index
-JITFRAME_FIXED_SIZE = 16 + 16
-# 16 GPR + 16 VFP Regs # 20 if we want to use 4 extra x19..x22
+JITFRAME_FIXED_SIZE = 16 + 8
+# 16 GPR + 8 VFP Regs # 20 if we want to use 4 extra x19..x22
diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -822,8 +822,8 @@
if value.is_imm():
self.mc.gen_load_int(loc.value, value.getint())
elif value.is_imm_float():
- self.mc.gen_load_int(r.ip.value, value.getint())
- self.mc.VLDR(loc.value, r.ip.value)
+ self.mc.gen_load_int(r.ip0.value, value.getint())
+ self.mc.LDR_di(loc.value, r.ip0.value, 0)
def _mov_stack_to_loc(self, prev_loc, loc):
offset = prev_loc.value
@@ -834,7 +834,13 @@
assert 0 <= offset <= (1<<15) - 1
self.mc.LDR_ri(loc.value, r.fp.value, offset)
return
- xxx
+ if loc.is_vfp_reg():
+ assert prev_loc.type == FLOAT, 'trying to load from an \
+ incompatible location into a float register'
+ assert 0 <= offset <= (1 << 15) - 1
+ self.mc.LDR_di(loc.value, r.fp.value, offset)
+ return
+ assert False
# elif loc.is_vfp_reg():
# assert prev_loc.type == FLOAT, 'trying to load from an \
# incompatible location into a float register'
@@ -932,12 +938,8 @@
return self._store_core_reg(mc, source, base, ofs)
def _store_vfp_reg(self, mc, source, base, ofs):
- if check_imm_arg(ofs, VMEM_imm_size):
- mc.VSTR(source.value, base.value, imm=ofs, cond=cond)
- else:
- mc.gen_load_int(helper.value, ofs, cond=cond)
- mc.ADD_rr(helper.value, base.value, helper.value, cond=cond)
- mc.VSTR(source.value, helper.value, cond=cond)
+ assert ofs <= (1 << 15) - 1
+ mc.STR_di(source.value, base.value, ofs)
def _store_core_reg(self, mc, source, base, ofs):
# uses r.ip1 as a temporary
diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -171,6 +171,22 @@
base = 0b10001011000 | (s << 8)
self.write32((base << 21) | (rm << 16) | (rn << 5) | (rd))
+ def FADD_dd(self, rd, rn, rm):
+ base = 0b00011110011
+ self.write32((base << 21) | (rm << 16) | (0b001010 << 10) | (rn << 5) | rd)
+
+ def FSUB_dd(self, rd, rn, rm):
+ base = 0b00011110011
+ self.write32((base << 21) | (rm << 16) | (0b001110 << 10) | (rn << 5) | rd)
+
+ def FMUL_dd(self, rd, rn, rm):
+ base = 0b00011110011
+ self.write32((base << 21) | (rm << 16) | (0b000010 << 10) | (rn << 5) | rd)
+
+ def FDIV_dd(self, rd, rn, rm):
+ base = 0b00011110011
+ self.write32((base << 21) | (rm << 16) | (0b000110 << 10) | (rn << 5) | rd)
+
def SUB_rr(self, rd, rn, rm, s=0):
base = 0b11001011001 | (s << 8)
self.write32((base << 21) | (rm << 16) | (0b11 << 13) | (rn << 5) | (rd))
diff --git a/rpython/jit/backend/aarch64/locations.py b/rpython/jit/backend/aarch64/locations.py
--- a/rpython/jit/backend/aarch64/locations.py
+++ b/rpython/jit/backend/aarch64/locations.py
@@ -114,6 +114,32 @@
return self.type == FLOAT
+class ConstFloatLoc(AssemblerLocation):
+ """This class represents an imm float value which is stored in memory at
+ the address stored in the field value"""
+ _immutable_ = True
+ width = WORD
+ type = FLOAT
+
+ def __init__(self, value):
+ self.value = value
+
+ def getint(self):
+ return self.value
+
+ def __repr__(self):
+ return "imm_float(stored at %d)" % (self.value)
+
+ def is_imm_float(self):
+ return True
+
+ def as_key(self): # a real address + 1
+ return self.value | 1
+
+ def is_float(self):
+ return True
+
+
class ZeroRegister(AssemblerLocation):
_immutable_ = True
diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -211,6 +211,22 @@
emit_op_cast_ptr_to_int = _genop_same_as
emit_op_cast_int_to_ptr = _genop_same_as
+ def emit_op_float_add(self, op, arglocs):
+ arg1, arg2, res = arglocs
+ self.mc.FADD_dd(res.value, arg1.value, arg2.value)
+
+ def emit_op_float_sub(self, op, arglocs):
+ arg1, arg2, res = arglocs
+ self.mc.FSUB_dd(res.value, arg1.value, arg2.value)
+
+ def emit_op_float_mul(self, op, arglocs):
+ arg1, arg2, res = arglocs
+ self.mc.FMUL_dd(res.value, arg1.value, arg2.value)
+
+ def emit_op_float_truediv(self, op, arglocs):
+ arg1, arg2, res = arglocs
+ self.mc.FDIV_dd(res.value, arg1.value, arg2.value)
+
def emit_op_load_from_gc_table(self, op, arglocs):
res_loc, = arglocs
index = op.getarg(0).getint()
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -19,11 +19,11 @@
from rpython.jit.backend.llsupport.gcmap import allocate_gcmap
from rpython.jit.backend.llsupport.descr import CallDescr
from rpython.jit.codewriter.effectinfo import EffectInfo
+from rpython.jit.codewriter import longlong
from rpython.rlib.rarithmetic import r_uint
-
class TempInt(TempVar):
type = INT
@@ -438,7 +438,22 @@
return [reg]
prepare_comp_op_int_is_true = prepare_comp_unary
- prepare_comp_op_int_is_zero = prepare_comp_unary
+ prepare_comp_op_int_is_zero = prepare_comp_unary
+
+ # --------------------------------- floats --------------------------
+
+ def prepare_two_regs_op(self, op):
+ loc1 = self.make_sure_var_in_reg(op.getarg(0))
+ loc2 = self.make_sure_var_in_reg(op.getarg(1))
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op)
+ return [loc1, loc2, res]
+
+ prepare_op_float_add = prepare_two_regs_op
+ prepare_op_float_sub = prepare_two_regs_op
+ prepare_op_float_mul = prepare_two_regs_op
+ prepare_op_float_truediv = prepare_two_regs_op
# --------------------------------- fields --------------------------
More information about the pypy-commit
mailing list