[pypy-commit] pypy arm64: fixes

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96752:b5abcfa99f96
Date: 2019-06-05 11:10 +0000
http://bitbucket.org/pypy/pypy/changeset/b5abcfa99f96/

Log:	fixes

diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -209,6 +209,22 @@
         index = op.getarg(0).getint()
         self.load_from_gc_table(res_loc.value, index)
 
+    def emit_op_load_effective_address(self, op, arglocs):
+        self._gen_address(arglocs[4], arglocs[0], arglocs[1], arglocs[3].value,
+                          arglocs[2].value)
+
+   # result = base_loc  + (scaled_loc << scale) + static_offset
+    def _gen_address(self, result, base_loc, scaled_loc, scale=0, static_offset=0):
+        assert scaled_loc.is_core_reg()
+        assert base_loc.is_core_reg()
+        if scale > 0:
+            self.mc.LSL_ri(r.ip0.value, scaled_loc.value, scale)
+            scaled_loc = r.ip0
+        else:
+            scaled_loc = scaled_loc
+        self.mc.ADD_rr(result.value, base_loc.value, scaled_loc.value)
+        self.mc.ADD_ri(result.value, result.value, static_offset)
+
     def emit_op_debug_merge_point(self, op, arglocs):
         pass
     
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -180,9 +180,8 @@
         operations = cpu.gc_ll_descr.rewrite_assembler(cpu, operations,
                                                        allgcrefs)
         # compute longevity of variables
-        longevity, last_real_usage = compute_vars_longevity(inputargs, operations)
+        longevity = compute_vars_longevity(inputargs, operations)
         self.longevity = longevity
-        self.last_real_usage = last_real_usage
         fm = self.frame_manager
         asm = self.assembler
         self.vfprm = VFPRegisterManager(longevity, fm, asm)
@@ -602,7 +601,7 @@
         position = self.rm.position
         for arg in inputargs:
             assert not isinstance(arg, Const)
-            if self.last_real_usage.get(arg, -1) <= position:
+            if self.longevity[arg].is_last_real_use_before(position):
                 self.force_spill_var(arg)
 
         #
@@ -724,6 +723,13 @@
         resloc = self.force_allocate_reg(op)
         return [resloc]
 
+    def prepare_op_load_effective_address(self, op):
+        args = op.getarglist()
+        arg0 = self.make_sure_var_in_reg(args[0], args)
+        arg1 = self.make_sure_var_in_reg(args[1], args)
+        res = self.force_allocate_reg(op)
+        return [arg0, arg1, args[2], args[3], res]
+
     def prepare_op_jump(self, op):
         assert self.jump_target_descr is None
         descr = op.getdescr()
diff --git a/rpython/jit/metainterp/resoperation.py b/rpython/jit/metainterp/resoperation.py
--- a/rpython/jit/metainterp/resoperation.py
+++ b/rpython/jit/metainterp/resoperation.py
@@ -1057,6 +1057,7 @@
     'LOAD_FROM_GC_TABLE/1/r',    # only emitted by rewrite.py
     #
     'LOAD_EFFECTIVE_ADDRESS/4/i', # only emitted by rewrite.py, shortcut for x86
+    # res = arg0 + (arg1 << arg3) + arg2
     #
     '_ALWAYS_PURE_LAST',  # ----- end of always_pure operations -----