[pypy-commit] pypy arm64: merge

[fijal]

Author: fijal
Branch: arm64
Changeset: r96916:c6d1d6d6b8c4
Date: 2019-07-02 12:34 +0200
http://bitbucket.org/pypy/pypy/changeset/c6d1d6d6b8c4/

Log:	merge

diff --git a/rpython/jit/backend/aarch64/TODO b/rpython/jit/backend/aarch64/TODO
--- a/rpython/jit/backend/aarch64/TODO
+++ b/rpython/jit/backend/aarch64/TODO
@@ -3,3 +3,10 @@
 * guard_nonnull_class - think about a better way
 * cond_call and following guard_exception
 * stack check
+
+
+We can try to make generate_quick_failure() emit two instructions less:
+the two store_reg() [one in generate_quick_failure and the other in
+push_gcmap].  Instead we'd load the values in known unused registers,
+and the store_regs would occur inside self.failure_recovery_code
+(which 'target' points to).
diff --git a/rpython/jit/backend/aarch64/arch.py b/rpython/jit/backend/aarch64/arch.py
--- a/rpython/jit/backend/aarch64/arch.py
+++ b/rpython/jit/backend/aarch64/arch.py
@@ -8,5 +8,7 @@
 # A jitframe is a jit.backend.llsupport.llmodel.jitframe.JITFRAME
 # Stack frame fixed area
 # Currently only the force_index
-JITFRAME_FIXED_SIZE = 16 + 2 + 8
-# 18 GPR + 8 VFP Regs # 20 if we want to use 4 extra x19..x22
+NUM_MANAGED_REGS = 16
+NUM_VFP_REGS = 8
+JITFRAME_FIXED_SIZE = NUM_MANAGED_REGS + NUM_VFP_REGS
+# 16 GPR + 8 VFP Regs, for now
diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -611,10 +611,10 @@
             # tid is in x0
             # length is in x1
             # gcmap in ip1
-            # itemsize in ip0
+            # itemsize in ip2
             mc.MOV_rr(r.x2.value, r.x1.value)
             mc.MOV_rr(r.x1.value, r.x0.value)
-            mc.MOV_rr(r.x0.value, r.ip0.value) # load itemsize, ip0 now free
+            mc.MOV_rr(r.x0.value, r.ip2.value) # load itemsize, ip2 now free
         # store the gc pattern
         ofs = self.cpu.get_ofs_of_frame_field('jf_gcmap')
         mc.STR_ri(r.ip1.value, r.fp.value, ofs)
@@ -775,7 +775,7 @@
         if kind == rewrite.FLAG_ARRAY:
             self.mc.gen_load_int(r.x0.value, arraydescr.tid)
             self.regalloc_mov(lengthloc, r.x1)
-            self.mc.gen_load_int(r.ip0.value, itemsize)
+            self.mc.gen_load_int(r.ip2.value, itemsize)
             addr = self.malloc_slowpath_varsize
         else:
             if kind == rewrite.FLAG_STR:
diff --git a/rpython/jit/backend/aarch64/registers.py b/rpython/jit/backend/aarch64/registers.py
--- a/rpython/jit/backend/aarch64/registers.py
+++ b/rpython/jit/backend/aarch64/registers.py
@@ -11,7 +11,7 @@
 
 vfpregisters = [VFPRegisterLocation(i) for i in range(32)]
 all_vfp_regs = vfpregisters[:8]
-all_regs = registers[:16]+ [x19, x20] #, x21, x22]
+all_regs = registers[:14]+ [x19, x20] #, x21, x22]
 
 lr = x30
 fp = x29
@@ -20,6 +20,8 @@
 # nor we use them for regalloc
 ip1 = x17
 ip0 = x16
+ip2 = x15
+ip3 = x14   # not used so far, but 'caller_resp' needs to be even-length anyway
 
 callee_saved_registers = [x19, x20] # , x21, x22]
 vfp_argument_regs = caller_vfp_resp = all_vfp_regs[:8]
@@ -31,4 +33,4 @@
 
 argument_regs = [x0, x1, x2, x3, x4, x5, x6, x7]
 callee_resp = [x19, x20] # ,x21, x22]
-caller_resp = argument_regs + [x8, x9, x10, x11, x12, x13, x14, x15]
+caller_resp = argument_regs + [x8, x9, x10, x11, x12, x13]
diff --git a/rpython/jit/backend/aarch64/runner.py b/rpython/jit/backend/aarch64/runner.py
--- a/rpython/jit/backend/aarch64/runner.py
+++ b/rpython/jit/backend/aarch64/runner.py
@@ -10,7 +10,7 @@
     """ARM 64"""
     backend_name = "aarch64"
     frame_reg = r.fp
-    all_reg_indexes = range(16) + [-1, -1, -1, 16, 17]
+    all_reg_indexes = range(14) + [-1, -1, -1, -1, -1, 14, 15]
     gen_regs = r.all_regs
     float_regs = VFPRegisterManager.all_regs
     supports_floats = True
@@ -61,3 +61,9 @@
         return CPU_ARM64.cast_adr_to_int(adr)
     cast_ptr_to_int._annspecialcase_ = 'specialize:arglltype(0)'
     cast_ptr_to_int = staticmethod(cast_ptr_to_int)
+
+
+for _i, _r in enumerate(r.all_regs):
+    assert CPU_ARM64.all_reg_indexes[_r.value] == _i
+from rpython.jit.backend.aarch64 import arch
+assert arch.NUM_MANAGED_REGS == len(r.all_regs)