[pypy-commit] pypy arm64: (fijal, arigo)

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r95795:35539313ed06
Date: 2019-02-04 15:57 +0000
http://bitbucket.org/pypy/pypy/changeset/35539313ed06/

Log:	(fijal, arigo)

	slow progress

diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -143,6 +143,9 @@
         pass
 
     def _build_stack_check_slowpath(self):
+        self.stack_check_slowpath = 0  #XXX
+
+    def _check_frame_depth_debug(self, mc):
         pass
 
     def reserve_gcref_table(self, allgcrefs):
@@ -167,25 +170,24 @@
             self.mc.BL(self.stack_check_slowpath, c=c.HI)      # call if ip > lr
 
     def _call_header(self):
-        stack_size = WORD #alignment
-        stack_size += len(r.callee_saved_registers) * WORD
+        stack_size = (len(r.callee_saved_registers) + 2) * WORD
+        self.mc.STP_rr_preindex(r.fp.value, r.lr.value, r.sp.value, -stack_size)
+        for i in range(0, len(r.callee_saved_registers), 2):
+            self.mc.STP_rri(r.callee_saved_registers[i].value,
+                            r.callee_saved_registers[i + 1].value,
+                            r.sp.value,
+                            (i + 2) * WORD)
+        
+        #self.saved_threadlocal_addr = 0   # at offset 0 from location 'sp'
+        # ^^^XXX save it from register x1 into some place
         if self.cpu.supports_floats:
-            stack_size += len(r.callee_saved_vfp_registers) * 2 * WORD
-
-        # push all callee saved registers including lr; and push r1 as
-        # well, which contains the threadlocal_addr argument.  Note that
-        # we're pushing a total of 10 words, which keeps the stack aligned.
-        self.mc.PUSH([reg.value for reg in r.callee_saved_registers] +
-                                                        [r.r1.value])
-        self.saved_threadlocal_addr = 0   # at offset 0 from location 'sp'
-        if self.cpu.supports_floats:
+            XXX
             self.mc.VPUSH([reg.value for reg in r.callee_saved_vfp_registers])
             self.saved_threadlocal_addr += (
                 len(r.callee_saved_vfp_registers) * 2 * WORD)
-        assert stack_size % 8 == 0 # ensure we keep alignment
 
-        # set fp to point to the JITFRAME
-        self.mc.MOV_rr(r.fp.value, r.r0.value)
+        # set fp to point to the JITFRAME, passed in argument 'x0'
+        self.mc.MOV_rr(r.fp.value, r.x0.value)
         #
         gcrootmap = self.cpu.gc_ll_descr.gcrootmap
         if gcrootmap and gcrootmap.is_shadow_stack:
diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -1,6 +1,8 @@
 
 from rpython.jit.backend.llsupport.asmmemmgr import BlockBuilderMixin
 from rpython.jit.backend.aarch64.locations import RegisterLocation
+from rpython.jit.backend.aarch64 import registers as r
+
 
 class AbstractAarch64Builder(object):
     def write32(self, word):
@@ -19,6 +21,27 @@
         self.write32((base << 22) | ((0x7F & (offset >> 3)) << 15) |
                      (reg2 << 10) | (rn << 5) | reg1)
 
+    def STP_rri(self, reg1, reg2, rn, offset):
+        base = 0b1010100100
+        assert -512 <= offset < 512
+        assert offset & 0x7 == 0
+        self.write32((base << 22) | ((0x7F & (offset >> 3)) << 15) |
+                     (reg2 << 10) | (rn << 5) | reg1)
+
+    def MOV_rr(self, rd, rn):
+        self.ORR_rr(rd, r.xzr.value, rn)
+
+    def ORR_rr(self, rd, rn, rm):
+        base = 0b10101010000
+        self.write32((base << 21) | (rm << 16) |
+                     (rn << 5) | rd)
+
+    def ADD_ri(self, rd, rn, constant):
+        base = 0b1001000100
+        assert 0 <= constant < 4096
+        self.write32((base << 22) | (constant << 10) |
+                     (rn << 5) | rd)
+
 class InstrBuilder(BlockBuilderMixin, AbstractAarch64Builder):
 
     def __init__(self, arch_version=7):
diff --git a/rpython/jit/backend/aarch64/registers.py b/rpython/jit/backend/aarch64/registers.py
--- a/rpython/jit/backend/aarch64/registers.py
+++ b/rpython/jit/backend/aarch64/registers.py
@@ -4,7 +4,7 @@
 
 
 registers = [RegisterLocation(i) for i in range(31)]
-sp = wzr = ZeroRegister()
+sp = xzr = ZeroRegister()
 [x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10,
  x11, x12, x13, x14, x15, x16, x17, x18, x19, x20,
  x21, x22, x23, x24, x25, x26, x27, x28, x29, x30] = registers
@@ -18,8 +18,6 @@
 ip1 = x17
 ip0 = x16
 
-callee_resp = [x19, x20, x21, x22, fp]
+callee_saved_registers = [x19, x20, x21, x22]
 
 argument_regs = caller_resp = [x0, x1, x2, x3, x4, x5, x6, x7]
-
-callee_saved_registers = callee_resp + [lr]
diff --git a/rpython/jit/backend/aarch64/test/test_instr_builder.py b/rpython/jit/backend/aarch64/test/test_instr_builder.py
--- a/rpython/jit/backend/aarch64/test/test_instr_builder.py
+++ b/rpython/jit/backend/aarch64/test/test_instr_builder.py
@@ -30,7 +30,18 @@
     @given(r1=st.sampled_from(r.registers),
            r2=st.sampled_from(r.registers),
            offset=st.integers(min_value=-64, max_value=63))
-    def test_call_header(self, r1, r2, offset):
+    def test_STP_rr(self, r1, r2, offset):
         cb = CodeBuilder()
         cb.STP_rr_preindex(r1.value, r2.value, r.sp.value, offset * 8)
         assert cb.hexdump() == assemble("STP %r, %r, [sp, %d]!" % (r1, r2, offset * 8))
+        cb = CodeBuilder()
+        cb.STP_rri(r1.value, r2.value, r.sp.value, offset * 8)
+        assert cb.hexdump() == assemble("STP %r, %r, [sp, %d]" % (r1, r2, offset * 8))
+
+    @settings(max_examples=20)
+    @given(r1=st.sampled_from(r.registers),
+           r2=st.sampled_from(r.registers))
+    def test_MOV_rr(self, r1, r2):
+        cb = CodeBuilder()
+        cb.MOV_rr(r1.value, r2.value)
+        assert cb.hexdump() == assemble("MOV %r, %r" % (r1, r2))