[pypy-commit] pypy arm64: more calling

[fijal]

Author: fijal
Branch: arm64
Changeset: r96534:26809d94a756
Date: 2019-04-22 12:25 +0200
http://bitbucket.org/pypy/pypy/changeset/26809d94a756/

Log:	more calling

diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -717,10 +717,23 @@
         else:
             XXX
 
+    def _mov_imm_to_loc(self, prev_loc, loc):
+        assert loc.is_core_reg()
+        self.mc.gen_load_int(loc.value, prev_loc.value)
+
     def new_stack_loc(self, i, tp):
         base_ofs = self.cpu.get_baseofs_of_frame_field()
         return StackLocation(i, get_fp_offset(base_ofs, i), tp)
 
+    def mov_loc_to_raw_stack(self, loc, pos):
+        if loc.is_core_reg():
+            self.mc.STR_ri(loc.value, r.sp.value, pos)
+        elif loc.is_stack():
+            self.mc.LDR_ri(r.ip0.value, r.fp.value, loc.value)
+            self.mc.STR_ri(r.ip0.value, r.sp.value, pos)
+        else:
+            assert False, "wrong loc"
+
     def regalloc_mov(self, prev_loc, loc):
         """Moves a value from a previous location to some other location"""
         if prev_loc.is_imm():
@@ -733,8 +746,6 @@
             self._mov_imm_float_to_loc(prev_loc, loc)
         elif prev_loc.is_vfp_reg():
             self._mov_vfp_reg_to_loc(prev_loc, loc)
-        elif prev_loc.is_raw_sp():
-            self._mov_raw_sp_to_loc(prev_loc, loc)
         else:
             assert 0, 'unsupported case'
     mov_loc_loc = regalloc_mov
diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -11,13 +11,6 @@
 
 class AbstractAarch64Builder(object):
     # just copied some values from https://gist.github.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a
-    immr_imms = {
-        32: (0b111011, 0b000000),
-        56: (0b111101, 0b000010),
-        48: (0b111100, 0b000001),
-        16: (0b111100, 0b000000),
-    }
-
     def write32(self, word):
         self.writechar(chr(word & 0xFF))
         self.writechar(chr((word >> 8) & 0xFF))
@@ -139,12 +132,22 @@
         base = 0b10001010000
         self.write32((base << 21) | (rm << 16) | (rn << 5) | rd)
 
+    def AND_ri(self, rd, rn, immed):
+        assert immed == 0xFF # just one value for now, don't feel like
+        # understanding IMMR/IMMS quite yet
+        base = 0b1001001001
+        immr = 0b000000
+        imms = 0b000111
+        self.write32((base << 22) | (immr << 16) | (imms << 10) | (rn << 5) | rd)
+
     def LSL_rr(self, rd, rn, rm):
         base = 0b10011010110
         self.write32((base << 21) | (rm << 16) | (0b001000 << 10) | (rn << 5) | rd)
 
     def LSL_ri(self, rd, rn, shift):
-        immr, imms = self.immr_imms[shift]
+        assert 0 <= shift <= 63
+        immr = 64 - shift
+        imms = immr - 1
         base = 0b1101001101
         self.write32((base << 22) | (immr << 16) | (imms << 10) | (rn << 5) | rd)
 
@@ -153,10 +156,19 @@
         self.write32((base << 21) | (rm << 16) | (0b001010 << 10) | (rn << 5) | rd)
 
     def ASR_ri(self, rd, rn, shift):
-        immr, imms = self.immr_imms[shift]
+        assert 0 <= shift <= 63
+        imms = 0b111111
+        immr = shift
         base = 0b1001001101
         self.write32((base << 22) | (immr << 16) | (imms << 10) | (rn << 5) | rd)
 
+    def LSR_ri(self, rd, rn, shift):
+        assert 0 <= shift <= 63
+        imms = 0b111111
+        immr = shift
+        base = 0b1101001101
+        self.write32((base << 22) | (immr << 16) | (imms << 10) | (rn << 5) | rd)
+
     def LSR_rr(self, rd, rn, rm):
         base = 0b10011010110
         self.write32((base << 21) | (rm << 16) | (0b001001 << 10) | (rn << 5) | rd)