[pypy-commit] pypy default: An attempt to find a general fix for arm/regalloc. In this backend (and not
arigo
pypy.commits at gmail.com
Fri Apr 5 07:53:41 EDT 2019
Author: Armin Rigo <arigo at tunes.org>
Branch:
Changeset: r96420:a243e4e0b21c
Date: 2019-04-05 13:49 +0200
http://bitbucket.org/pypy/pypy/changeset/a243e4e0b21c/
Log: An attempt to find a general fix for arm/regalloc. In this backend
(and not the others as far as I can tell), there can be a mixture of
calls to make_sure_var_in_reg() and get_scratch_reg(). Try to make
sure that none of these calls will accidentally return a register
that a previous call already returned.
diff --git a/rpython/jit/backend/arm/regalloc.py b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -84,6 +84,8 @@
return []
class ARMRegisterManager(RegisterManager):
+ FORBID_TEMP_BOXES = True
+
def return_constant(self, v, forbidden_vars=[], selected_reg=None):
self._check_type(v)
if isinstance(v, Const):
@@ -94,7 +96,7 @@
else:
tp = INT
loc = self.get_scratch_reg(tp,
- self.temp_boxes + forbidden_vars,
+ forbidden_vars,
selected_reg=selected_reg)
immvalue = self.convert_to_imm(v)
self.assembler.load(loc, immvalue)
@@ -129,9 +131,9 @@
def get_scratch_reg(self, type=FLOAT, forbidden_vars=[], selected_reg=None):
assert type == FLOAT # for now
box = TempFloat()
- self.temp_boxes.append(box)
reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
selected_reg=selected_reg)
+ self.temp_boxes.append(box)
return reg
@@ -164,9 +166,9 @@
box = TempInt()
else:
box = TempPtr()
- self.temp_boxes.append(box)
reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
selected_reg=selected_reg)
+ self.temp_boxes.append(box)
return reg
def get_free_reg(self):
diff --git a/rpython/jit/backend/llsupport/regalloc.py b/rpython/jit/backend/llsupport/regalloc.py
--- a/rpython/jit/backend/llsupport/regalloc.py
+++ b/rpython/jit/backend/llsupport/regalloc.py
@@ -280,6 +280,7 @@
no_lower_byte_regs = []
save_around_call_regs = []
frame_reg = None
+ FORBID_TEMP_BOXES = False
def __init__(self, longevity, frame_manager=None, assembler=None):
self.free_regs = self.all_regs[:]
@@ -441,6 +442,8 @@
reg = self.reg_bindings[next]
if next in forbidden_vars:
continue
+ if self.FORBID_TEMP_BOXES and next in self.temp_boxes:
+ continue
if selected_reg is not None:
if reg is selected_reg:
return next
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