[pypy-commit] pypy ppc-vsx-support: same patch for x86
plan_rich
pypy.commits at gmail.com
Mon Sep 19 08:44:23 EDT 2016
Author: Richard Plangger <planrichi at gmail.com>
Branch: ppc-vsx-support
Changeset: r87227:93b3c662735a
Date: 2016-09-19 14:43 +0200
http://bitbucket.org/pypy/pypy/changeset/93b3c662735a/
Log: same patch for x86
diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -16,6 +16,7 @@
from rpython.rtyper import rclass
from rpython.rlib.jit import AsmInfo
from rpython.jit.backend.model import CompiledLoopToken
+from rpython.jit.backend.x86.jump import remap_frame_layout_mixed
from rpython.jit.backend.x86.regalloc import (RegAlloc, get_ebp_ofs,
gpr_reg_mgr_cls, xmm_reg_mgr_cls)
from rpython.jit.backend.llsupport.regalloc import (get_scale, valid_addressing_size)
@@ -682,17 +683,25 @@
bridge_accum_info = bridge_accum_info.next()
guard_accum_info = guard_accum_info.next()
- # register mapping is most likely NOT valid, thus remap it in this
- # short piece of assembler
+ # register mapping is most likely NOT valid, thus remap it
+ src_locations1 = []
+ dst_locations1 = []
+ src_locations2 = []
+ dst_locations2 = []
+
+ # Build the four lists
assert len(guard_locs) == len(bridge_locs)
- for i,gloc in enumerate(guard_locs):
- bloc = bridge_locs[i]
- bstack = bloc.location_code() == 'b'
- gstack = gloc.location_code() == 'b'
- if bstack and gstack:
- pass
- elif gloc is not bloc:
- self.mov(gloc, bloc)
+ for i,src_loc in enumerate(guard_locs):
+ dst_loc = bridge_locs[i]
+ if not src_loc.is_fp_reg():
+ src_locations1.append(src_loc)
+ dst_locations1.append(dst_loc)
+ else:
+ src_locations2.append(src_loc)
+ dst_locations2.append(dst_loc)
+ remap_frame_layout_mixed(self, src_locations1, dst_locations1, r.SCRATCH,
+ src_locations2, dst_locations2, r.FP_SCRATCH)
+
offset = self.mc.get_relative_pos()
self.mc.JMP_l(0)
self.mc.writeimm32(0)
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