[pypy-commit] pypy default: resolve an issue. s390x does not put the values at the same position in the register as x86 does
plan_rich
pypy.commits at gmail.com
Fri Nov 4 15:35:46 EDT 2016
Author: Richard Plangger <planrichi at gmail.com>
Branch:
Changeset: r88140:fae41cc92dca
Date: 2016-11-04 20:31 +0100
http://bitbucket.org/pypy/pypy/changeset/fae41cc92dca/
Log: resolve an issue. s390x does not put the values at the same position
in the register as x86 does
diff --git a/rpython/jit/backend/llsupport/vector_ext.py b/rpython/jit/backend/llsupport/vector_ext.py
--- a/rpython/jit/backend/llsupport/vector_ext.py
+++ b/rpython/jit/backend/llsupport/vector_ext.py
@@ -208,6 +208,7 @@
TR_FLOAT_2 = TypeRestrict(FLOAT, 4, 2)
TR_DOUBLE_2 = TypeRestrict(FLOAT, 8, 2)
TR_INT32_2 = TypeRestrict(INT, 4, 2)
+TR_INT64_2 = TypeRestrict(INT, 8, 2)
OR_MSTF_I = OpMatchSizeTypeFirst([TR_ANY_INTEGER, TR_ANY_INTEGER])
OR_MSTF_F = OpMatchSizeTypeFirst([TR_ANY_FLOAT, TR_ANY_FLOAT])
diff --git a/rpython/jit/backend/zarch/vector_ext.py b/rpython/jit/backend/zarch/vector_ext.py
--- a/rpython/jit/backend/zarch/vector_ext.py
+++ b/rpython/jit/backend/zarch/vector_ext.py
@@ -2,11 +2,10 @@
from rpython.jit.metainterp.history import (ConstInt, INT, FLOAT)
from rpython.jit.backend.llsupport.descr import (ArrayDescr,
unpack_arraydescr)
-from rpython.jit.metainterp.resoperation import VectorOp
+from rpython.jit.metainterp.resoperation import VectorOp, rop
from rpython.rlib.objectmodel import we_are_translated
from rpython.rtyper.lltypesystem.lloperation import llop
from rpython.rtyper.lltypesystem import lltype
-from rpython.jit.backend.llsupport.vector_ext import VectorExt
from rpython.jit.backend.zarch.detect_feature import detect_simd_z
import rpython.jit.backend.zarch.registers as r
import rpython.jit.backend.zarch.conditions as c
@@ -17,6 +16,8 @@
from rpython.jit.codewriter import longlong
from rpython.rlib.objectmodel import always_inline
from rpython.jit.backend.zarch.arch import WORD
+from rpython.jit.backend.llsupport.vector_ext import (VectorExt,
+ OpRestrict, TR_INT64_2)
def not_implemented(msg):
msg = '[zarch/vector_ext] %s\n' % msg
@@ -51,6 +52,7 @@
self.enable(16, accum=True)
asm.setup_once_vector()
self._setup = True
+ZSIMDVectorExt.TR_MAPPING[rop.VEC_CAST_INT_TO_FLOAT] = OpRestrict([TR_INT64_2])
class VectorAssembler(object):
_mixin_ = True
@@ -125,10 +127,18 @@
self.mc.VX(resloc, loc0, loc1)
def emit_vec_int_signext(self, op, arglocs, regalloc):
- resloc, loc0 = arglocs
+ resloc, loc0, osizeloc, nsizeloc = arglocs
# signext is only allowed if the data type sizes do not change.
# e.g. [byte,byte] = sign_ext([byte, byte]), a simple move is sufficient!
- self.regalloc_mov(loc0, resloc)
+ osize = osizeloc.value
+ nsize = nsizeloc.value
+ if osize == nsize:
+ self.regalloc_mov(loc0, resloc)
+ elif (osize == 4 and nsize == 8) or (osize == 8 and nsize == 4):
+ self.mc.VLGV(r.SCRATCH, loc0, l.addr(0), l.itemsize_to_mask(osize))
+ self.mc.VLVG(resloc, r.SCRATCH, l.addr(0), l.itemsize_to_mask(nsize))
+ self.mc.VLGV(r.SCRATCH, loc0, l.addr(1), l.itemsize_to_mask(osize))
+ self.mc.VLVG(resloc, r.SCRATCH, l.addr(1), l.itemsize_to_mask(nsize))
def emit_vec_float_abs(self, op, arglocs, regalloc):
resloc, argloc, sizeloc = arglocs
@@ -291,6 +301,8 @@
srcidx = srcidxloc.value
count = countloc.value
size = sizeloc.value
+ assert isinstance(op, VectorOp)
+ newsize = op.bytesize
if count == 1:
if resloc.is_core_reg():
assert sourceloc.is_vector_reg()
@@ -301,7 +313,7 @@
assert resloc.is_vector_reg()
index = l.addr(residx)
self.mc.VLR(resloc, vecloc)
- self.mc.VLVG(resloc, sourceloc, index, l.itemsize_to_mask(size))
+ self.mc.VLVG(resloc, sourceloc, index, l.itemsize_to_mask(newsize))
else:
assert resloc.is_vector_reg()
assert sourceloc.is_vector_reg()
@@ -311,7 +323,7 @@
# load from sourceloc into GP reg and store back into resloc
self.mc.VLGV(r.SCRATCH, sourceloc, sindex, l.itemsize_to_mask(size))
rindex = l.addr(j + residx)
- self.mc.VLVG(resloc, r.SCRATCH, rindex, l.itemsize_to_mask(size))
+ self.mc.VLVG(resloc, r.SCRATCH, rindex, l.itemsize_to_mask(newsize))
emit_vec_unpack_i = emit_vec_pack_i
@@ -461,9 +473,10 @@
def prepare_vec_int_signext(self, op):
assert isinstance(op, VectorOp)
a0 = op.getarg(0)
+ assert isinstance(a0, VectorOp)
loc0 = self.ensure_vector_reg(a0)
resloc = self.force_allocate_vector_reg(op)
- return [resloc, loc0]
+ return [resloc, loc0, imm(a0.bytesize), imm(op.bytesize)]
def prepare_vec_arith_unary(self, op):
assert isinstance(op, VectorOp)
diff --git a/rpython/jit/metainterp/optimizeopt/schedule.py b/rpython/jit/metainterp/optimizeopt/schedule.py
--- a/rpython/jit/metainterp/optimizeopt/schedule.py
+++ b/rpython/jit/metainterp/optimizeopt/schedule.py
@@ -383,8 +383,8 @@
# 1)
args[i] = vecop # a)
assemble_scattered_values(state, pack, args, i) # c)
+ position_values(state, restrict, pack, args, i, pos) # d)
crop_vector(state, oprestrict, restrict, pack, args, i) # b)
- position_values(state, restrict, pack, args, i, pos) # d)
restrict.check(args[i])
def prepare_fail_arguments(state, pack, left, vecop):
diff --git a/rpython/jit/metainterp/test/test_vector.py b/rpython/jit/metainterp/test/test_vector.py
--- a/rpython/jit/metainterp/test/test_vector.py
+++ b/rpython/jit/metainterp/test/test_vector.py
@@ -878,21 +878,21 @@
a = raw_storage_getitem(rffi.INT,va,j)
b = raw_storage_getitem(rffi.DOUBLE,vb,i)
c = rffi.cast(rffi.DOUBLE,a)+b
- raw_storage_setitem(vc, i, rffi.cast(rffi.DOUBLE,c))
+ raw_storage_setitem(vc, i, c)
j += 4
i += 8
va = alloc_raw_storage(4*30, zero=True)
vb = alloc_raw_storage(8*30, zero=True)
for i,v in enumerate([1]*30):
- raw_storage_setitem(vb, i*4, rffi.cast(rffi.INT,v))
+ raw_storage_setitem(va, i*4, rffi.cast(rffi.INT,v))
for i,v in enumerate([-9.0]*30):
raw_storage_setitem(vb, i*8, rffi.cast(rffi.DOUBLE,v))
vc = alloc_raw_storage(8*30, zero=True)
self.meta_interp(f, [8*30, va, vb, vc], vec=True)
for i in range(30):
- assert raw_storage_getitem(rffi.INT,vc,i*8) == 8.0
+ assert raw_storage_getitem(rffi.DOUBLE,vc,i*8) == -8.0
free_raw_storage(va)
free_raw_storage(vb)
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