[pypy-commit] pypy remove-raisingops: Kill everything about DIV, MOD and UDIV from the arm backend
arigo
pypy.commits at gmail.com
Thu May 26 05:17:32 EDT 2016
Author: Armin Rigo <arigo at tunes.org>
Branch: remove-raisingops
Changeset: r84705:9b69a27a838b
Date: 2016-05-26 11:12 +0200
http://bitbucket.org/pypy/pypy/changeset/9b69a27a838b/
Log: Kill everything about DIV, MOD and UDIV from the arm backend
diff --git a/rpython/jit/backend/arm/codebuilder.py b/rpython/jit/backend/arm/codebuilder.py
--- a/rpython/jit/backend/arm/codebuilder.py
+++ b/rpython/jit/backend/arm/codebuilder.py
@@ -1,6 +1,5 @@
from rpython.jit.backend.arm import conditions as cond
from rpython.jit.backend.arm import registers as reg
-from rpython.jit.backend.arm import support
from rpython.jit.backend.arm.arch import WORD, PC_OFFSET
from rpython.jit.backend.arm.instruction_builder import define_instructions
from rpython.jit.backend.llsupport.asmmemmgr import BlockBuilderMixin
@@ -17,17 +16,6 @@
sandboxsafe=True)
-def binary_helper_call(name):
- function = getattr(support, 'arm_%s' % name)
-
- def f(self, c=cond.AL):
- """Generates a call to a helper function, takes its
- arguments in r0 and r1, result is placed in r0"""
- addr = rffi.cast(lltype.Signed, function)
- self.BL(addr, c)
- return f
-
-
class AbstractARMBuilder(object):
def __init__(self, arch_version=7):
self.arch_version = arch_version
@@ -348,10 +336,6 @@
self.write32(c << 28
| 0x157ff05f)
- DIV = binary_helper_call('int_div')
- MOD = binary_helper_call('int_mod')
- UDIV = binary_helper_call('uint_div')
-
FMDRR = VMOV_cr # uh, there are synonyms?
FMRRD = VMOV_rc
diff --git a/rpython/jit/backend/arm/helper/assembler.py b/rpython/jit/backend/arm/helper/assembler.py
--- a/rpython/jit/backend/arm/helper/assembler.py
+++ b/rpython/jit/backend/arm/helper/assembler.py
@@ -46,20 +46,6 @@
f.__name__ = 'emit_op_%s' % name
return f
-def gen_emit_op_by_helper_call(name, opname):
- helper = getattr(InstrBuilder, opname)
- def f(self, op, arglocs, regalloc, fcond):
- assert fcond is not None
- if op.type != 'v':
- regs = r.caller_resp[1:] + [r.ip]
- else:
- regs = r.caller_resp
- with saved_registers(self.mc, regs, r.caller_vfp_resp):
- helper(self.mc, fcond)
- return fcond
- f.__name__ = 'emit_op_%s' % name
- return f
-
def gen_emit_cmp_op(name, true_cond):
def f(self, op, arglocs, regalloc, fcond):
l0, l1, res = arglocs
diff --git a/rpython/jit/backend/arm/helper/regalloc.py b/rpython/jit/backend/arm/helper/regalloc.py
--- a/rpython/jit/backend/arm/helper/regalloc.py
+++ b/rpython/jit/backend/arm/helper/regalloc.py
@@ -72,25 +72,6 @@
res = self.force_allocate_reg_or_cc(op)
return [loc1, loc2, res]
-def prepare_op_by_helper_call(name):
- def f(self, op, fcond):
- assert fcond is not None
- a0 = op.getarg(0)
- a1 = op.getarg(1)
- arg1 = self.rm.make_sure_var_in_reg(a0, selected_reg=r.r0)
- arg2 = self.rm.make_sure_var_in_reg(a1, selected_reg=r.r1)
- assert arg1 == r.r0
- assert arg2 == r.r1
- if not isinstance(a0, Const) and self.stays_alive(a0):
- self.force_spill_var(a0)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- self.after_call(op)
- self.possibly_free_var(op)
- return []
- f.__name__ = name
- return f
-
def prepare_int_cmp(self, op, fcond):
assert fcond is not None
boxes = list(op.getarglist())
diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -3,7 +3,7 @@
from rpython.jit.backend.arm import registers as r
from rpython.jit.backend.arm import shift
from rpython.jit.backend.arm.arch import WORD, DOUBLE_WORD, JITFRAME_FIXED_SIZE
-from rpython.jit.backend.arm.helper.assembler import (gen_emit_op_by_helper_call,
+from rpython.jit.backend.arm.helper.assembler import (
gen_emit_op_unary_cmp,
gen_emit_op_ri,
gen_emit_cmp_op,
@@ -132,10 +132,6 @@
self.guard_success_cc = c.VC
return fcond
- emit_op_int_floordiv = gen_emit_op_by_helper_call('int_floordiv', 'DIV')
- emit_op_int_mod = gen_emit_op_by_helper_call('int_mod', 'MOD')
- emit_op_uint_floordiv = gen_emit_op_by_helper_call('uint_floordiv', 'UDIV')
-
emit_op_int_and = gen_emit_op_ri('int_and', 'AND')
emit_op_int_or = gen_emit_op_ri('int_or', 'ORR')
emit_op_int_xor = gen_emit_op_ri('int_xor', 'EOR')
diff --git a/rpython/jit/backend/arm/regalloc.py b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -7,7 +7,7 @@
from rpython.jit.backend.arm import conditions as c
from rpython.jit.backend.arm import locations
from rpython.jit.backend.arm.locations import imm, get_fp_offset
-from rpython.jit.backend.arm.helper.regalloc import (prepare_op_by_helper_call,
+from rpython.jit.backend.arm.helper.regalloc import (
prepare_unary_cmp,
prepare_op_ri,
prepare_int_cmp,
@@ -478,10 +478,6 @@
resloc = self.force_allocate_reg(op)
return [argloc, imm(numbytes), resloc]
- prepare_op_int_floordiv = prepare_op_by_helper_call('int_floordiv')
- prepare_op_int_mod = prepare_op_by_helper_call('int_mod')
- prepare_op_uint_floordiv = prepare_op_by_helper_call('unit_floordiv')
-
prepare_op_int_and = prepare_op_ri('int_and')
prepare_op_int_or = prepare_op_ri('int_or')
prepare_op_int_xor = prepare_op_ri('int_xor')
diff --git a/rpython/jit/backend/arm/support.py b/rpython/jit/backend/arm/support.py
deleted file mode 100644
--- a/rpython/jit/backend/arm/support.py
+++ /dev/null
@@ -1,54 +0,0 @@
-from rpython.rtyper.lltypesystem import lltype, rffi, llmemory
-from rpython.rlib.rarithmetic import r_uint
-from rpython.translator.tool.cbuild import ExternalCompilationInfo
-
-eci = ExternalCompilationInfo(post_include_bits=["""
-static int pypy__arm_int_div(int a, int b) {
- return a/b;
-}
-static unsigned int pypy__arm_uint_div(unsigned int a, unsigned int b) {
- return a/b;
-}
-static int pypy__arm_int_mod(int a, int b) {
- return a % b;
-}
-"""])
-
-
-def arm_int_div_emulator(a, b):
- return int(a / float(b))
-arm_int_div_sign = lltype.Ptr(
- lltype.FuncType([lltype.Signed, lltype.Signed], lltype.Signed))
-arm_int_div = rffi.llexternal(
- "pypy__arm_int_div", [lltype.Signed, lltype.Signed], lltype.Signed,
- _callable=arm_int_div_emulator,
- compilation_info=eci,
- _nowrapper=True, elidable_function=True)
-
-
-def arm_uint_div_emulator(a, b):
- return r_uint(a) / r_uint(b)
-arm_uint_div_sign = lltype.Ptr(
- lltype.FuncType([lltype.Unsigned, lltype.Unsigned], lltype.Unsigned))
-arm_uint_div = rffi.llexternal(
- "pypy__arm_uint_div", [lltype.Unsigned, lltype.Unsigned], lltype.Unsigned,
- _callable=arm_uint_div_emulator,
- compilation_info=eci,
- _nowrapper=True, elidable_function=True)
-
-
-def arm_int_mod_emulator(a, b):
- sign = 1
- if a < 0:
- a = -1 * a
- sign = -1
- if b < 0:
- b = -1 * b
- res = a % b
- return sign * res
-arm_int_mod_sign = arm_int_div_sign
-arm_int_mod = rffi.llexternal(
- "pypy__arm_int_mod", [lltype.Signed, lltype.Signed], lltype.Signed,
- _callable=arm_int_mod_emulator,
- compilation_info=eci,
- _nowrapper=True, elidable_function=True)
diff --git a/rpython/jit/backend/arm/test/test_arch.py b/rpython/jit/backend/arm/test/test_arch.py
deleted file mode 100644
--- a/rpython/jit/backend/arm/test/test_arch.py
+++ /dev/null
@@ -1,23 +0,0 @@
-from rpython.jit.backend.arm import support
-
-def test_mod():
- assert support.arm_int_mod(10, 2) == 0
- assert support.arm_int_mod(11, 2) == 1
- assert support.arm_int_mod(11, 3) == 2
-
-def test_mod2():
- assert support.arm_int_mod(-10, 2) == 0
- assert support.arm_int_mod(-11, 2) == -1
- assert support.arm_int_mod(-11, 3) == -2
-
-def test_mod3():
- assert support.arm_int_mod(10, -2) == 0
- assert support.arm_int_mod(11, -2) == 1
- assert support.arm_int_mod(11, -3) == 2
-
-
-def test_div():
- assert support.arm_int_div(-7, 2) == -3
- assert support.arm_int_div(9, 2) == 4
- assert support.arm_int_div(10, 5) == 2
-
diff --git a/rpython/jit/backend/arm/test/test_assembler.py b/rpython/jit/backend/arm/test/test_assembler.py
--- a/rpython/jit/backend/arm/test/test_assembler.py
+++ b/rpython/jit/backend/arm/test/test_assembler.py
@@ -193,32 +193,6 @@
self.a.gen_func_epilog()
assert run_asm(self.a) == 61
- def test_DIV(self):
- self.a.gen_func_prolog()
- self.a.mc.MOV_ri(r.r0.value, 123)
- self.a.mc.MOV_ri(r.r1.value, 2)
- self.a.mc.DIV()
- self.a.gen_func_epilog()
- assert run_asm(self.a) == 61
-
- def test_DIV2(self):
- self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r0.value, -110)
- self.a.mc.gen_load_int(r.r1.value, 3)
- self.a.mc.DIV()
- self.a.gen_func_epilog()
- assert run_asm(self.a) == -36
-
- def test_DIV3(self):
- self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r8.value, 110)
- self.a.mc.gen_load_int(r.r9.value, -3)
- self.a.mc.MOV_rr(r.r0.value, r.r8.value)
- self.a.mc.MOV_rr(r.r1.value, r.r9.value)
- self.a.mc.DIV()
- self.a.gen_func_epilog()
- assert run_asm(self.a) == -36
-
def test_bl_with_conditional_exec(self):
functype = lltype.Ptr(lltype.FuncType([lltype.Signed], lltype.Signed))
call_addr = rffi.cast(lltype.Signed, llhelper(functype, callme))
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