[pypy-commit] pypy ppc-vsx-support: more changes and impl. of lxvd2x test passes now
plan_rich
pypy.commits at gmail.com
Tue Jun 14 08:32:50 EDT 2016
Author: Richard Plangger <planrichi at gmail.com>
Branch: ppc-vsx-support
Changeset: r85158:d326e675ae9d
Date: 2016-06-14 14:31 +0200
http://bitbucket.org/pypy/pypy/changeset/d326e675ae9d/
Log: more changes and impl. of lxvd2x test passes now
diff --git a/rpython/jit/backend/ppc/codebuilder.py b/rpython/jit/backend/ppc/codebuilder.py
--- a/rpython/jit/backend/ppc/codebuilder.py
+++ b/rpython/jit/backend/ppc/codebuilder.py
@@ -1,4 +1,5 @@
import os
+
from rpython.jit.backend.ppc.ppc_form import PPCForm as Form
from rpython.jit.backend.ppc.locations import RegisterLocation
from rpython.jit.backend.ppc.ppc_field import ppc_fields
@@ -60,6 +61,7 @@
XFL = Form("FM", "frB", "XO1", "Rc")
XFX = Form("CRM", "rS", "XO1")
XLL = Form("LL", "XO1")
+XX1 = Form("vrT", "rA", "rB", "XO1")
MI = Form("rA", "rS", "SH", "MB", "ME", "Rc")
MB = Form("rA", "rS", "rB", "MB", "ME", "Rc")
@@ -266,6 +268,7 @@
lwbrx = XD(31, XO1=534)
lwzux = XD(31, XO1=55)
lwzx = XD(31, XO1=23)
+ lxvd2x = XX1(31, XO1=844)
mcrfs = Form("crfD", "crfS", "XO1")(63, XO1=64)
mcrxr = Form("crfD", "XO1")(31, XO1=512)
diff --git a/rpython/jit/backend/ppc/locations.py b/rpython/jit/backend/ppc/locations.py
--- a/rpython/jit/backend/ppc/locations.py
+++ b/rpython/jit/backend/ppc/locations.py
@@ -1,4 +1,4 @@
-from rpython.jit.metainterp.history import INT, FLOAT
+from rpython.jit.metainterp.history import INT, FLOAT, VECTOR
import sys
# cannot import from arch.py, currently we have a circular import
@@ -75,6 +75,24 @@
def as_key(self):
return self.value + 100
+class VectorRegisterLocation(AssemblerLocation):
+ _immutable_ = True
+ width = WORD
+ type = VECTOR
+
+ def __init__(self, value):
+ self.value = value
+
+ def __repr__(self):
+ return 'vr%d' % self.value
+
+ def is_reg(self):
+ return True
+
+ def as_key(self):
+ return self.value + 132
+
+
class ImmLocation(AssemblerLocation):
_immutable_ = True
width = WORD
diff --git a/rpython/jit/backend/ppc/ppc_field.py b/rpython/jit/backend/ppc/ppc_field.py
--- a/rpython/jit/backend/ppc/ppc_field.py
+++ b/rpython/jit/backend/ppc/ppc_field.py
@@ -43,6 +43,7 @@
"spr": (11, 20),
"TO": ( 6, 10),
"UIMM": (16, 31),
+ "vrT": (6, 31, 'unsigned', regname._V, 'overlap'),
"XO1": (21, 30),
"XO2": (22, 30),
"XO3": (26, 30),
@@ -100,6 +101,17 @@
def decode(self, inst):
value = super(sh, self).decode(inst)
return (value & 32) << 5 | (value >> 10 & 31)
+
+class tx(Field):
+ def encode(self, value):
+ value = (value & 31) << 20 | (value & 32) >> 5
+ return super(tx, self).encode(value)
+ def decode(self, inst):
+ value = super(tx, self).decode(inst)
+ return (value & 32) << 5 | (value >> 20 & 31)
+ def r(self):
+ import pdb; pdb.set_trace()
+ return super(tx, self).r()
# other special fields?
ppc_fields = {
@@ -109,6 +121,7 @@
"mbe": mbe("mbe", *fields["mbe"]),
"sh": sh("sh", *fields["sh"]),
"spr": spr("spr", *fields["spr"]),
+ "vrT": tx("vrT", *fields["vrT"]),
}
for f in fields:
diff --git a/rpython/jit/backend/ppc/rassemblermaker.py b/rpython/jit/backend/ppc/rassemblermaker.py
--- a/rpython/jit/backend/ppc/rassemblermaker.py
+++ b/rpython/jit/backend/ppc/rassemblermaker.py
@@ -46,6 +46,9 @@
elif field.name == 'sh':
body.append('sh1 = (%s & 31) << 10 | (%s & 32) >> 5' % (value, value))
value = 'sh1'
+ elif field.name == 'vrT':
+ body.append('vrT1 = (%s & 31) << 20 | (%s & 32) >> 5' % (value, value))
+ value = 'vrT1'
if isinstance(field, IField):
body.append('v |= ((%3s >> 2) & r_uint(%#05x)) << 2' % (value, field.mask))
else:
diff --git a/rpython/jit/backend/ppc/register.py b/rpython/jit/backend/ppc/register.py
--- a/rpython/jit/backend/ppc/register.py
+++ b/rpython/jit/backend/ppc/register.py
@@ -1,8 +1,9 @@
from rpython.jit.backend.ppc.locations import (RegisterLocation,
- FPRegisterLocation)
+ FPRegisterLocation, VectorRegisterLocation)
ALL_REGS = [RegisterLocation(i) for i in range(32)]
ALL_FLOAT_REGS = [FPRegisterLocation(i) for i in range(32)]
+ALL_VECTOR_REGS = [VectorRegisterLocation(i) for i in range(64)]
r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16,\
r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31\
@@ -12,6 +13,13 @@
f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, f31\
= ALL_FLOAT_REGS
+vr0, vr1, vr2, vr3, vr4, vr5, vr6, vr7, vr8, vr9, vr10, vr11, vr12, vr13, \
+ vr14, vr15, vr16, vr17, vr18, vr19, vr20, vr21, vr22, vr23, vr24, vr25, \
+ vr26, vr27, vr28, vr29, vr30, vr31, vr32, vr33, vr34, vr35, vr36, vr37, \
+ vr38, vr39, vr40, vr41, vr42, vr43, vr44, vr45, vr46, vr47, vr48, \
+ vr49, vr50, vr51, vr52, vr53, vr54, vr55, vr56, vr57, vr58, vr59, vr60, \
+ vr61, vr62, vr63 = ALL_VECTOR_REGS
+
NONVOLATILES = [r14, r15, r16, r17, r18, r19, r20, r21, r22, r23,
r24, r25, r26, r27, r28, r29, r30, r31]
VOLATILES = [r3, r4, r5, r6, r7, r8, r9, r10, r11, r12]
diff --git a/rpython/jit/backend/ppc/regname.py b/rpython/jit/backend/ppc/regname.py
--- a/rpython/jit/backend/ppc/regname.py
+++ b/rpython/jit/backend/ppc/regname.py
@@ -6,6 +6,10 @@
def __repr__(self):
return "fr%s"%(super(_F, self).__repr__(),)
__str__ = __repr__
+class _V(int):
+ def __repr__(self):
+ return "vr%s"%(super(_V, self).__repr__(),)
+ __str__ = __repr__
r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, \
r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, \
@@ -15,4 +19,11 @@
fr13, fr14, fr15, fr16, fr17, fr18, fr19, fr20, fr21, fr22, \
fr23, fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31 = map(_F, range(32))
+vr0, vr1, vr2, vr3, vr4, vr5, vr6, vr7, vr8, vr9, vr10, vr11, vr12, vr13, \
+ vr14, vr15, vr16, vr17, vr18, vr19, vr20, vr21, vr22, vr23, vr24, vr25, \
+ vr26, vr27, vr28, vr29, vr30, vr31, vr32, vr33, vr34, vr35, vr36, vr37, \
+ vr38, vr39, vr40, vr41, vr42, vr43, vr44, vr45, vr46, vr47, vr48, \
+ vr49, vr50, vr51, vr52, vr53, vr54, vr55, vr56, vr57, vr58, vr59, vr60, \
+ vr61, vr62, vr63 = map(_V, range(64))
+
crf0, crf1, crf2, crf3, crf4, crf5, crf6, crf7 = range(8)
diff --git a/rpython/jit/backend/ppc/test/test_vector_instr.py b/rpython/jit/backend/ppc/test/test_vector_instr.py
--- a/rpython/jit/backend/ppc/test/test_vector_instr.py
+++ b/rpython/jit/backend/ppc/test/test_vector_instr.py
@@ -30,8 +30,8 @@
expected = test(self, a, *[rffi.cast(lltype.Signed, m) for m in memory_ptrs])
f = a.get_assembler_function()
f()
- for type, expect, ptr in expected:
- value = rffi.cast(lltype.CArrayPtr(type), ptr)[0]
+ for expect, type, ptr in expected:
+ value = rffi.cast(rffi.CArrayPtr(type), ptr)[0]
assert value == expect
while memory_ptrs:
@@ -61,7 +61,7 @@
@vec_asmtest(memory=[(8, signed, [0,0])])
def test_unaligned_load(self, a, mem):
a.load_imm(r15, mem)
- a.lxvd2x(0, 15, mem)
+ a.lxvd2x(vr0.value, 0, r15.value)
a.blr()
return [ (0, signed, mem), (0, signed, mem+8) ]
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