[pypy-commit] pypy ppc-vsx-support: rpythonify detect_feature. it can now be done while running the vm,

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: ppc-vsx-support
Changeset: r85894:27e39abe0a99
Date: 2016-07-28 17:47 +0200
http://bitbucket.org/pypy/pypy/changeset/27e39abe0a99/

Log:	rpythonify detect_feature. it can now be done while running the vm,
	catchup some changes to the vectorizer model

diff --git a/rpython/jit/backend/x86/detect_feature.py b/rpython/jit/backend/x86/detect_feature.py
--- a/rpython/jit/backend/x86/detect_feature.py
+++ b/rpython/jit/backend/x86/detect_feature.py
@@ -3,13 +3,15 @@
 from rpython.rtyper.lltypesystem import lltype, rffi
 from rpython.rlib.rmmap import alloc, free
 
+CPU_ID_FUNC_PTR = lltype.Ptr(lltype.FuncType([], lltype.Signed))
+
 def cpu_info(instr):
     data = alloc(4096)
     pos = 0
     for c in instr:
         data[pos] = c
         pos += 1
-    fnptr = rffi.cast(lltype.Ptr(lltype.FuncType([], lltype.Signed)), data)
+    fnptr = rffi.cast(CPU_ID_FUNC_PTR, data)
     code = fnptr()
     free(data, 4096)
     return code
@@ -19,17 +21,17 @@
     return bool(code & (1<<25)) and bool(code & (1<<26))
 
 def cpu_id(eax = 1, ret_edx = True, ret_ecx = False):
-    asm = "\xB8" + struct.pack('I', eax) # MOV EAX, $eax
-    asm += ("\x53"                     # PUSH EBX
-            "\x0F\xA2"                 # CPUID
-            "\x5B"                     # POP EBX
-           )
+    asm = ["\xB8", chr(eax), "\x00\x00\x00", # MOV EAX, $eax
+           "\x53",                     # PUSH EBX
+           "\x0F\xA2",                 # CPUID
+           "\x5B",                     # POP EBX
+          ]
     if ret_edx:
-        asm += "\x92"                 # XCHG EAX, EDX
+        asm.append("\x92")             # XCHG EAX, EDX
     elif ret_ecx:
-        asm += "\x91"                 # XCHG EAX, ECX
-    asm += "\xC3"                     # RET
-    return cpu_info(asm)
+        asm.append("\x91")             # XCHG EAX, ECX
+    asm.append("\xC3")                 # RET
+    return cpu_info(''.join(asm))
 
 def detect_sse4_1(code=-1):
     if code == -1:
diff --git a/rpython/jit/backend/x86/runner.py b/rpython/jit/backend/x86/runner.py
--- a/rpython/jit/backend/x86/runner.py
+++ b/rpython/jit/backend/x86/runner.py
@@ -64,10 +64,6 @@
         if self.HAS_CODEMAP:
             self.codemap.setup()
         self.assembler.setup_once()
-        if self.vector_ext:
-            # TODO
-            pass
-            #self.vector_ext.
 
     @rgc.no_release_gil
     def finish_once(self):
diff --git a/rpython/jit/backend/x86/vector_ext.py b/rpython/jit/backend/x86/vector_ext.py
--- a/rpython/jit/backend/x86/vector_ext.py
+++ b/rpython/jit/backend/x86/vector_ext.py
@@ -59,7 +59,7 @@
         assert isinstance(arg, VectorOp)
         size = arg.bytesize
         temp = X86_64_XMM_SCRATCH_REG
-        load = arg.bytesize * arg.count - self.cpu.vector_register_size
+        load = arg.bytesize * arg.count - self.cpu.vector_ext.register_size
         assert load <= 0
         if true:
             self.mc.PXOR(temp, temp)