[pypy-commit] pypy s390x-backend: malloc_cond ported to s390x

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r81605:e16953ea7521
Date: 2016-01-07 11:11 +0100
http://bitbucket.org/pypy/pypy/changeset/e16953ea7521/

Log:	malloc_cond ported to s390x

diff --git a/rpython/jit/backend/zarch/assembler.py b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -942,7 +942,7 @@
         return start
 
     def _reload_frame_if_necessary(self, mc, shadowstack_reg=None):
-        # might trash the VOLATILE registers different from r3 and f1
+        # might trash the VOLATILE registers different from r2 and f0
         gcrootmap = self.cpu.gc_ll_descr.gcrootmap
         if gcrootmap:
             if gcrootmap.is_shadow_stack:
@@ -1013,18 +1013,6 @@
         self.mc.LMG(r.r6, r.r15, l.addr(6*WORD, r.SP))
         self.jmpto(r.r14)
 
-    def _push_all_regs_to_stack(self, mc, withfloats, callee_only=False):
-        # not used!!
-        # TODO remove if not needed
-        base_ofs = 2*WORD
-        if callee_only:
-            regs = ZARCHRegisterManager.save_around_call_regs
-        else:
-            regs = r.registers[2:]
-        mc.STMG(regs[0], regs[1], l.addr(base_ofs, r.SP))
-        if withfloats:
-            xxx
-
     def _push_all_regs_to_frame(self, mc, ignored_regs, withfloats, callee_only=False):
         # Push all general purpose registers
         base_ofs = self.cpu.get_baseofs_of_frame_field()
@@ -1193,6 +1181,56 @@
         ptr = rffi.cast(lltype.Signed, gcmap)
         mc.load_imm(reg, ptr)
 
+    def malloc_cond(self, nursery_free_adr, nursery_top_adr, size, gcmap):
+        assert size & (WORD-1) == 0     # must be correctly aligned
+
+        # We load into RES the address stored at nursery_free_adr. We
+        # calculate the new value for nursery_free_adr and store it in
+        # RSZ.  Then we load the address stored in nursery_top_adr
+        # into SCRATCH.  In the rare case where the value in RSZ is
+        # (unsigned) bigger than the one in SCRATCH we call
+        # malloc_slowpath.  In the common case where malloc_slowpath
+        # is not called, we must still write RSZ back into
+        # nursery_free_adr (r1); so we do it always, even if we called
+        # malloc_slowpath.
+
+        diff = nursery_top_adr - nursery_free_adr
+        assert check_imm_value(diff)
+        mc = self.mc
+        mc.load_imm(r.r1, nursery_free_adr)
+
+        mc.load(r.RES, r.r1, 0)          # load nursery_free
+        mc.load(r.SCRATCH2, r.r1, diff)  # load nursery_top
+
+        mc.LGR(r.RSZ, r.RES)
+        if check_imm_value(size):
+            mc.AGHI(r.RSZ, l.imm(size))
+        else:
+            mc.load_imm(r.SCRATCH, l.imm(size))
+            mc.AGR(r.RSZ, r.SCRATCH)
+
+        mc.cmp_op(r.RSZ, r.SCRATCH2, signed=False)
+
+        fast_jmp_pos = mc.currpos()
+        mc.reserve_cond_jump() # conditional jump, patched later
+
+
+        # new value of nursery_free_adr in RSZ and the adr of the new object
+        # in RES.
+        self.load_gcmap(mc, r.SCRATCH, gcmap)
+        # We are jumping to malloc_slowpath without a call through a function
+        # descriptor, because it is an internal call and "call" would trash
+        # r2 and r11
+        mc.branch_absolute(self.malloc_slowpath)
+
+        offset = mc.currpos() - fast_jmp_pos
+        pmc = OverwritingBuilder(mc, fast_jmp_pos, 1)
+        pmc.BRCL(c.LE, l.imm(offset))    # jump if LE (not GT), predicted to be true
+        pmc.overwrite()
+
+        mc.STG(r.RSZ, l.addr(0, r.r1))    # store into nursery_free
+
+
     def malloc_cond_varsize_frame(self, nursery_free_adr, nursery_top_adr,
                                   sizeloc, gcmap):
         xxx
diff --git a/rpython/jit/backend/zarch/codebuilder.py b/rpython/jit/backend/zarch/codebuilder.py
--- a/rpython/jit/backend/zarch/codebuilder.py
+++ b/rpython/jit/backend/zarch/codebuilder.py
@@ -198,6 +198,14 @@
         """
         self.BASR(r.RETURN, call_reg)
 
+    def reserve_cond_jump(self):
+        self.trap()        # conditional jump, patched later
+        self.write('\x00'*4)
+
+    def branch_absolute(self, addr):
+        self.load_imm(r.r14, addr)
+        self.BASR(r.r14, r.r14)
+
     def store_link(self):
         self.STG(r.RETURN, l.addr(14*WORD, r.SP))
 
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -7,6 +7,7 @@
         gen_emit_imm_pool_rr)
 from rpython.jit.backend.zarch.helper.regalloc import (check_imm,
         check_imm_value)
+from rpython.jit.metainterp.history import (ConstInt)
 from rpython.jit.backend.zarch.codebuilder import ZARCHGuardToken, InstrBuilder
 from rpython.jit.backend.llsupport import symbolic, jitframe
 import rpython.jit.backend.zarch.conditions as c
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -748,7 +748,6 @@
         return self._prepare_call_default(op)
 
     def prepare_call_malloc_nursery(self, op):
-        xxx
         self.rm.force_allocate_reg(op, selected_reg=r.RES)
         self.rm.temp_boxes.append(op)
         tmp_box = TempInt()
diff --git a/rpython/jit/backend/zarch/registers.py b/rpython/jit/backend/zarch/registers.py
--- a/rpython/jit/backend/zarch/registers.py
+++ b/rpython/jit/backend/zarch/registers.py
@@ -17,7 +17,7 @@
 SCRATCH2 = r0
 GPR_RETURN = r2
 RES = r2
-RSZ = r3
+RSZ = r6
 
 [f0,f1,f2,f3,f4,f5,f6,f7,f8,
  f9,f10,f11,f12,f13,f14,f15] = fpregisters