[pypy-commit] pypy s390x-backend: pair regalloc does not overwrite the variable binding anymore, but binds an the reigster to an additional parameter (e.g. the return value)
plan_rich
pypy.commits at gmail.com
Mon Jan 4 15:39:40 EST 2016
Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r81561:3c7888505b50
Date: 2016-01-04 21:38 +0100
http://bitbucket.org/pypy/pypy/changeset/3c7888505b50/
Log: pair regalloc does not overwrite the variable binding anymore, but
binds an the reigster to an additional parameter (e.g. the return
value)
diff --git a/rpython/jit/backend/test/runner_test.py b/rpython/jit/backend/test/runner_test.py
--- a/rpython/jit/backend/test/runner_test.py
+++ b/rpython/jit/backend/test/runner_test.py
@@ -535,11 +535,11 @@
return chr(ord(c) + ord(c1))
functions = [
- (func_int, lltype.Signed, types.sint, 655360, 655360),
- (func_int, lltype.Signed, types.sint, 655360, -293999429),
+ #(func_int, lltype.Signed, types.sint, 655360, 655360),
+ #(func_int, lltype.Signed, types.sint, 655360, -293999429),
(func_int, rffi.SHORT, types.sint16, 1213, 1213),
- (func_int, rffi.SHORT, types.sint16, 1213, -12020),
- (func_char, lltype.Char, types.uchar, 12, 12),
+ #(func_int, rffi.SHORT, types.sint16, 1213, -12020),
+ #(func_char, lltype.Char, types.uchar, 12, 12),
]
cpu = self.cpu
diff --git a/rpython/jit/backend/zarch/helper/regalloc.py b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -51,12 +51,11 @@
a1 = op.getarg(1)
if check_imm32(a0):
a0, a1 = a1, a0
- lr,lq = self.rm.ensure_even_odd_pair(a0, bind_first=False)
+ lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=False)
if check_imm32(a1):
l1 = imm(a1.getint())
else:
l1 = self.ensure_reg(a1)
- self.force_result_in_reg(op, a0)
self.free_op_vars()
return [lr, lq, l1]
@@ -66,11 +65,10 @@
a1 = op.getarg(1)
if isinstance(a0, Const):
poolloc = self.ensure_reg(a0)
- lr,lq = self.rm.ensure_even_odd_pair(op, bind_first=modulus, must_exist=False)
+ lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=modulus, must_exist=False)
self.assembler.mc.LG(lq, poolloc)
else:
- lr,lq = self.rm.ensure_even_odd_pair(a0, bind_first=modulus)
- self.rm.force_result_in_reg(op, a0)
+ lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=modulus)
l1 = self.ensure_reg(a1)
self.free_op_vars()
self.rm._check_invariants()
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -157,19 +157,19 @@
self.temp_boxes.append(box)
return reg
- def ensure_even_odd_pair(self, var, bind_first=True,
+ def ensure_even_odd_pair(self, var, bindvar, bind_first=True,
must_exist=True, load_loc_odd=True,
move_regs=True):
self._check_type(var)
prev_loc = self.loc(var, must_exist=must_exist)
var2 = TempVar()
- self.temp_boxes.append(var2)
if prev_loc is self.frame_reg:
return prev_loc
if bind_first:
- loc, loc2 = self.force_allocate_reg_pair(var, var2, self.temp_boxes)
+ loc, loc2 = self.force_allocate_reg_pair(bindvar, var2, self.temp_boxes)
else:
- loc, loc2 = self.force_allocate_reg_pair(var2, var, self.temp_boxes)
+ loc, loc2 = self.force_allocate_reg_pair(var2, bindvar, self.temp_boxes)
+ self.temp_boxes.append(var2)
assert loc.is_even() and loc2.is_odd()
if move_regs and prev_loc is not loc2:
if load_loc_odd:
@@ -179,12 +179,8 @@
return loc, loc2
def force_allocate_reg_pair(self, var, var2, forbidden_vars=[], selected_reg=None):
- """ Forcibly allocate a register for the new variable v.
- It must not be used so far. If we don't have a free register,
- spill some other variable, according to algorithm described in
- '_pick_variable_to_spill'.
-
- Will not spill a variable from 'forbidden_vars'.
+ """ Forcibly allocate a register for the new variable var.
+ var will have an even register (var2 will have an odd register).
"""
self._check_type(var)
self._check_type(var2)
@@ -207,6 +203,8 @@
candidates.append(odd)
i -= 1
continue
+ assert var not in self.reg_bindings
+ assert var2 not in self.reg_bindings
self.reg_bindings[var] = even
self.reg_bindings[var2] = odd
del self.free_regs[i]
@@ -490,10 +488,14 @@
if not we_are_translated() and opnum == -127:
self._consider_force_spill(op)
else:
+ print("regalloc before", self.rm.free_regs, self.rm.reg_bindings)
+ print(op)
arglocs = prepare_oplist[opnum](self, op)
asm_operations[opnum](self.assembler, op, arglocs, self)
self.free_op_vars()
self.possibly_free_var(op)
+ print("regalloc after", self.rm.free_regs, self.rm.reg_bindings)
+ print""
self.rm._check_invariants()
self.fprm._check_invariants()
if self.assembler.mc.get_relative_pos() > self.limit_loop_break:
@@ -908,11 +910,11 @@
def prepare_zero_array(self, op):
itemsize, ofs, _ = unpack_arraydescr(op.getdescr())
- base_loc, length_loc = self.rm.ensure_even_odd_pair(op.getarg(0),
+ base_loc, length_loc = self.rm.ensure_even_odd_pair(op.getarg(0), op,
bind_first=True, must_exist=False, load_loc_odd=False)
tempvar = TempInt()
self.rm.temp_boxes.append(tempvar)
- pad_byte, _ = self.rm.ensure_even_odd_pair(tempvar,
+ pad_byte, _ = self.rm.ensure_even_odd_pair(tempvar, tempvar,
bind_first=True, must_exist=False, move_regs=False)
startindex_loc = self.ensure_reg_or_16bit_imm(op.getarg(1))
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