[pypy-commit] pypy optresult-unroll: merge

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: optresult-unroll
Changeset: r79490:922650aeb8e6
Date: 2015-09-06 22:19 +0200
http://bitbucket.org/pypy/pypy/changeset/922650aeb8e6/

Log:	merge

diff --git a/rpython/jit/backend/arm/helper/assembler.py b/rpython/jit/backend/arm/helper/assembler.py
--- a/rpython/jit/backend/arm/helper/assembler.py
+++ b/rpython/jit/backend/arm/helper/assembler.py
@@ -50,7 +50,7 @@
     helper = getattr(InstrBuilder, opname)
     def f(self, op, arglocs, regalloc, fcond):
         assert fcond is not None
-        if op.result:
+        if op.type != 'v':
             regs = r.caller_resp[1:] + [r.ip]
         else:
             regs = r.caller_resp
diff --git a/rpython/jit/backend/arm/helper/regalloc.py b/rpython/jit/backend/arm/helper/regalloc.py
--- a/rpython/jit/backend/arm/helper/regalloc.py
+++ b/rpython/jit/backend/arm/helper/regalloc.py
@@ -1,13 +1,13 @@
 from rpython.jit.backend.arm import conditions as c
 from rpython.jit.backend.arm import registers as r
-from rpython.jit.metainterp.history import Const, FLOAT
+from rpython.jit.metainterp.history import Const, ConstInt, FLOAT
 from rpython.rlib.objectmodel import we_are_translated
 
 VMEM_imm_size=0x3FC
 default_imm_size=0xFF
 
 def check_imm_arg(arg, size=default_imm_size, allow_zero=True):
-    assert not isinstance(arg, Const)
+    assert not isinstance(arg, Const)     # because it must be an int :-)
     if not we_are_translated():
         if not isinstance(arg, int):
             import pdb; pdb.set_trace()
@@ -19,7 +19,7 @@
     return i <= size and lower_bound
 
 def check_imm_box(arg, size=0xFF, allow_zero=True):
-    if isinstance(arg, Const):
+    if isinstance(arg, ConstInt):
         return check_imm_arg(arg.getint(), size, allow_zero)
     return False
 
@@ -111,7 +111,7 @@
 def prepare_unary_cmp(self, op, fcond):
     assert fcond is not None
     a0 = op.getarg(0)
-    assert isinstance(a0, Box)
+    assert not isinstance(a0, Const)
     reg = self.make_sure_var_in_reg(a0)
     self.possibly_free_vars_for_op(op)
     res = self.force_allocate_reg_or_cc(op)