[pypy-commit] pypy s390x-backend: implemented signext, test_runner checking signext passes

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80757:d09527f603f6
Date: 2015-11-18 15:58 +0100
http://bitbucket.org/pypy/pypy/changeset/d09527f603f6/

Log:	implemented signext, test_runner checking signext passes

diff --git a/rpython/jit/backend/zarch/helper/regalloc.py b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -152,7 +152,7 @@
     self.free_op_vars()
     return [l0, l1]
 
-def prepare_unary_op(self, op):
+def prepare_unary_cmp(self, op):
     a0 = op.getarg(0)
     assert not isinstance(a0, ConstInt)
     l0 = self.ensure_reg(a0)
@@ -160,3 +160,11 @@
     res = self.force_allocate_reg_or_cc(op)
     self.free_op_vars()
     return [l0, res]
+
+def prepare_unary_op(self, op):
+    a0 = op.getarg(0)
+    assert not isinstance(a0, ConstInt)
+    l0 = self.ensure_reg(a0)
+    self.force_result_in_reg(op, a0)
+    self.free_op_vars()
+    return [l0]
diff --git a/rpython/jit/backend/zarch/instructions.py b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -129,6 +129,11 @@
     'LOCGR':  ('rrf_c',    ['\xB9','\xE2']),
     'LOCG':   ('rsy_b',    ['\xEB','\xE2']),
 
+    # load for sign ext
+    'LGBR':   ('rre',      ['\xB9','\x06']),
+    'LGHR':   ('rre',      ['\xB9','\x07']),
+    'LGFR':   ('rre',      ['\xB9','\x14']),
+
     # store memory
     'STMG':    ('rsy_a',   ['\xEB','\x24']),
     'ST':      ('rx',    ['\x50']),
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -114,14 +114,26 @@
             #self.mc.AGR(lr, l1)
 
     def emit_int_invert(self, op, arglocs, regalloc):
-        l0, _ = arglocs
+        l0 = arglocs
         assert not l0.is_imm()
         self.mc.XG(l0, l.pool(self.pool.constant_64_ones))
 
     def emit_int_neg(self, op, arglocs, regalloc):
-        l0, _ = arglocs
+        l0 = arglocs
         self.mc.LCGR(l0, l0)
 
+    def emit_int_signext(self, op, arglocs, regalloc):
+        l0, = arglocs
+        extend_from = op.getarg(1).getint()
+        if extend_from == 1:
+            self.mc.LGBR(l0, l0)
+        elif extend_from == 2:
+            self.mc.LGHR(l0, l0)
+        elif extend_from == 4:
+            self.mc.LGFR(l0, l0)
+        else:
+            raise AssertionError(extend_from)
+
     def emit_int_is_zero(self, op, arglocs, regalloc):
         l0, res = arglocs
         self.mc.CGHI(l0, l.imm(0))
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -646,10 +646,13 @@
     prepare_uint_ge = helper.generate_cmp_op(signed=False)
     prepare_uint_gt = helper.generate_cmp_op(signed=False)
 
-    prepare_int_is_zero = helper.prepare_unary_op
-    prepare_int_is_true = helper.prepare_unary_op
+    prepare_int_is_zero = helper.prepare_unary_cmp
+    prepare_int_is_true = helper.prepare_unary_cmp
+
     prepare_int_neg     = helper.prepare_unary_op
     prepare_int_invert  = helper.prepare_unary_op
+    prepare_int_signext = helper.prepare_unary_op
+
     prepare_int_force_ge_zero = helper.prepare_unary_op