[pypy-commit] pypy s390x-backend: reordered free registers and force result in register (wrong order double loaded values already in a register)

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80537:094ee6d25c63
Date: 2015-11-04 14:20 +0100
http://bitbucket.org/pypy/pypy/changeset/094ee6d25c63/

Log:	reordered free registers and force result in register (wrong order
	double loaded values already in a register)

diff --git a/rpython/jit/backend/zarch/helper/regalloc.py b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -17,8 +17,8 @@
         l1 = imm(a1.getint())
     else:
         l1 = self.ensure_reg(a1)
+    self.force_result_in_reg(op, a0)
     self.free_op_vars()
-    self.force_result_in_reg(op, a0)
     return [l0, l1]
 
 def prepare_int_sub(self, op):
@@ -28,8 +28,8 @@
         a0, a1 = a1, a0
     l0 = self.ensure_reg(a0)
     l1 = self.ensure_reg(a1)
+    self.force_result_in_reg(op, a0)
     self.free_op_vars()
-    self.force_result_in_reg(op, a0)
     return [l0, l1]
 
 def prepare_cmp_op(self, op):
@@ -42,8 +42,8 @@
         l1 = imm(a1.getint())
     else:
         l1 = self.ensure_reg(a1)
+    self.force_result_in_reg(op, a0)
     self.free_op_vars()
-    self.force_result_in_reg(op, a0)
     return [l0, l1]
 
 def prepare_binary_op(self, op):
@@ -51,6 +51,6 @@
     a1 = op.getarg(1)
     l0 = self.ensure_reg(a0)
     l1 = self.ensure_reg(a1)
+    self.force_result_in_reg(op, a0)
     self.free_op_vars()
-    self.force_result_in_reg(op, a0)
     return [l0, l1]