[pypy-commit] pypy s390x-backend: test drag along, found one bug (did not copy compare long instr bytes from manual)

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80515:4baab7a89095
Date: 2015-11-03 16:04 +0100
http://bitbucket.org/pypy/pypy/changeset/4baab7a89095/

Log:	test drag along, found one bug (did not copy compare long instr
	bytes from manual)

diff --git a/rpython/jit/backend/zarch/codebuilder.py b/rpython/jit/backend/zarch/codebuilder.py
--- a/rpython/jit/backend/zarch/codebuilder.py
+++ b/rpython/jit/backend/zarch/codebuilder.py
@@ -155,4 +155,5 @@
 
 # Used to build the MachineCodeBlockWrapper
 all_instructions = sorted([name for cls in _classes for name in cls.__dict__ \
-                          if name.split('_')[0].isupper() and '_' in name])
+                          if name.split('_')[0].isupper() and '_' in name and \
+                             not name.endswith('_byte_count')])
diff --git a/rpython/jit/backend/zarch/instructions.py b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -27,7 +27,7 @@
     'CGR':     ('rre',    ['\xB9','\x20']),
     'CG':      ('rxy',    ['\xE3','\x20']),
     'CLGR':    ('rre',    ['\xB9','\x21']),
-    'CLG':     ('rxy',    ['\xE3','\x20']),
+    'CLG':     ('rxy',    ['\xE3','\x21']),
     'CGHI':    ('ri',     ['\xA7','\x0F']),
 }
 
diff --git a/rpython/jit/backend/zarch/test/test_assembler.py b/rpython/jit/backend/zarch/test/test_assembler.py
--- a/rpython/jit/backend/zarch/test/test_assembler.py
+++ b/rpython/jit/backend/zarch/test/test_assembler.py
@@ -25,9 +25,6 @@
 
 CPU = getcpuclass()
 
-def byte_count(func):
-    return func._byte_count
-
 def BFL(value, short=False):
     if short:
         return struct.pack('f', value)
@@ -114,8 +111,8 @@
             is AssemblerZARCH.emit_int_add.im_func
 
     def test_byte_count_instr(self):
-        byte_count(self.mc.BRC) == 4
-        byte_count(self.mc.LG) == 6
+        assert self.mc.BRC_byte_count == 4
+        assert self.mc.LG_byte_count == 6
 
     def test_load_small_int_to_reg(self):
         self.a.mc.LGHI(reg.r2, loc.imm(123))
@@ -178,7 +175,7 @@
 
     def test_literal_pool(self):
         self.a.gen_func_prolog()
-        self.a.mc.BRAS(reg.r13, loc.imm(8 + byte_count(self.mc.BRAS)))
+        self.a.mc.BRAS(reg.r13, loc.imm(8 + self.mc.BRAS_byte_count))
         self.a.mc.write('\x08\x07\x06\x05\x04\x03\x02\x01')
         self.a.mc.LG(reg.r2, loc.addr(0, reg.r13))
         self.a.gen_func_epilog()