[pypy-commit] pypy vecopt: int expand 64 bit working

[plan_rich]

Author: Richard Plangger <rich at pasra.at>
Branch: vecopt
Changeset: r77868:812b3caa438c
Date: 2015-06-04 18:37 +0200
http://bitbucket.org/pypy/pypy/changeset/812b3caa438c/

Log:	int expand 64 bit working

diff --git a/pypy/module/micronumpy/test/test_zjit.py b/pypy/module/micronumpy/test/test_zjit.py
--- a/pypy/module/micronumpy/test/test_zjit.py
+++ b/pypy/module/micronumpy/test/test_zjit.py
@@ -196,6 +196,21 @@
         assert int(result) == 7+1+8+1+11+2+12+2
         self.check_vectorized(2, 2)
 
+    def define_int_expand():
+        return """
+        a = astype(|30|, int)
+        c = astype(|1|, int)
+        c[0] = 16
+        b = a + c
+        x1 = b -> 7
+        x2 = b -> 8
+        x1 + x2
+        """
+    def test_int_expand(self):
+        result = self.run("int_expand")
+        assert int(result) == 7+16+8+16
+        self.check_vectorized(2, 2)
+
     def define_int32_add_const():
         return """
         a = astype(|30|, int32)
diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -2638,8 +2638,13 @@
 
     def genop_vec_int_expand(self, op, arglocs, resloc):
         srcloc, sizeloc = arglocs
+        assert not srcloc.is_xmm
         size = sizeloc.value
-        raise NotImplementedError
+        if size == 8:
+            self.mc.PINSRQ_xri(resloc.value, srcloc.value, 0)
+            self.mc.PINSRQ_xri(resloc.value, srcloc.value, 1)
+        else:
+            raise NotImplementedError("missing size %d for int expand" % (size,))
 
     def genop_vec_int_pack(self, op, arglocs, resloc):
         resultloc, sourceloc, residxloc, srcidxloc, countloc, sizeloc = arglocs
diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -81,20 +81,6 @@
         rffi.cast(rffi.CArrayPtr(longlong.FLOATSTORAGE), adr)[1] = y
         return ConstFloatLoc(adr)
 
-    def expand_int(self, var, const):
-        assert isinstance(var, BoxVector)
-        if var.getsize() == 4:
-            loc = self.expand_single_float(const)
-        else:
-            loc = self.expand_double_float(const)
-        adr = self.assembler.datablockwrapper.malloc_aligned(16, 16)
-        x = c.getfloatstorage()
-        y = longlong.ZEROF
-        rffi.cast(rffi.CArrayPtr(longlong.FLOATSTORAGE), adr)[0] = x
-        rffi.cast(rffi.CArrayPtr(longlong.FLOATSTORAGE), adr)[1] = y
-        self.reg_bindings[var] = loc
-        return loc
-
     def expand_float(self, var, const):
         assert isinstance(var, BoxVector)
         if var.getsize() == 4:
@@ -1639,6 +1625,7 @@
         arg = op.getarg(0)
         if isinstance(arg, Const):
             resloc = self.xrm.expand_float(op.result, arg)
+            # TODO consider this
             return
         args = op.getarglist()
         resloc = self.xrm.force_result_in_reg(op.result, arg, args)
@@ -1649,13 +1636,14 @@
     def consider_vec_int_expand(self, op):
         arg = op.getarg(0)
         if isinstance(arg, Const):
-            resloc = self.xrm.expand_int(op.result, arg)
-            return
-        args = op.getarglist()
-        resloc = self.xrm.force_result_in_reg(op.result, arg, args)
+            srcloc = self.rm.convert_to_imm(arg)
+        else:
+            args = op.getarglist()
+            srcloc = self.make_sure_var_in_reg(arg, args)
+        resloc = self.xrm.force_allocate_reg(op.result, args)
         assert isinstance(op.result, BoxVector)
         size = op.result.getsize()
-        self.perform(op, [resloc, imm(size)], resloc)
+        self.perform(op, [srcloc, imm(size)], resloc)
 
     def consider_vec_int_signext(self, op):
         args = op.getarglist()