[pypy-commit] pypy default: Clarify a bit this logic

[arigo]

Author: Armin Rigo <arigo at tunes.org>
Branch: 
Changeset: r75756:f252c05d7308
Date: 2015-02-07 20:11 +0100
http://bitbucket.org/pypy/pypy/changeset/f252c05d7308/

Log:	Clarify a bit this logic

diff --git a/rpython/jit/backend/x86/rx86.py b/rpython/jit/backend/x86/rx86.py
--- a/rpython/jit/backend/x86/rx86.py
+++ b/rpython/jit/backend/x86/rx86.py
@@ -304,13 +304,20 @@
 REX_B = 1
 
 @specialize.arg(2)
-def encode_rex(mc, rexbyte, basevalue, orbyte):
+def encode_rex(mc, rexbyte, w, orbyte):
     if mc.WORD == 8:
         assert 0 <= rexbyte < 8
-        if basevalue != 0 or rexbyte != 0:
-            if basevalue == 0:
-                basevalue = 0x40
-            mc.writechar(chr(basevalue | rexbyte))
+        mc.writechar(chr(0x40 | w | rexbyte))
+    else:
+        assert rexbyte == 0
+    return 0
+
+ at specialize.arg(2)
+def encode_rex_opt(mc, rexbyte, _, orbyte):
+    if mc.WORD == 8:
+        assert 0 <= rexbyte < 8
+        if rexbyte != 0:
+            mc.writechar(chr(0x40 | rexbyte))
     else:
         assert rexbyte == 0
     return 0
@@ -322,9 +329,9 @@
 # the REX prefix in all cases.  It is only useful on instructions which
 # have an 8-bit register argument, to force access to the "sil" or "dil"
 # registers (as opposed to "ah-dh").
-rex_w  = encode_rex, 0, (0x40 | REX_W), None      # a REX.W prefix
-rex_nw = encode_rex, 0, 0, None                   # an optional REX prefix
-rex_fw = encode_rex, 0, 0x40, None                # a forced REX prefix
+rex_w  = encode_rex, 0, REX_W, None       # a REX.W prefix
+rex_nw = encode_rex_opt, 0, 0, None       # an optional REX prefix
+rex_fw = encode_rex, 0, 0, None           # a forced REX prefix
 
 # ____________________________________________________________