[pypy-commit] pypy s390x-backend: zero_array nearly passing, on some runs it still fails

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r81459:7ff79cde4286
Date: 2015-12-28 17:54 +0100
http://bitbucket.org/pypy/pypy/changeset/7ff79cde4286/

Log:	zero_array nearly passing, on some runs it still fails

diff --git a/rpython/jit/backend/test/runner_test.py b/rpython/jit/backend/test/runner_test.py
--- a/rpython/jit/backend/test/runner_test.py
+++ b/rpython/jit/backend/test/runner_test.py
@@ -65,6 +65,7 @@
     def execute_operations(self, inputargs, operations, result_type):
         looptoken = JitCellToken()
         self.cpu.compile_loop(inputargs, operations, looptoken)
+        #import pdb; pdb.set_trace()
         args = []
         for box in inputargs:
             if box.type == 'i':
@@ -5005,12 +5006,12 @@
             addr = llmemory.cast_ptr_to_adr(a)
             a_int = heaptracker.adr2int(addr)
             a_ref = lltype.cast_opaque_ptr(llmemory.GCREF, a)
-            for (start, length) in [(0,100)]:#3, (49, 49), (1, 98),
-                                    #(15, 9), (10, 10), (47, 0),
-                                    #(0, 4)]:
+            for (start, length) in [(0,100), (49, 49), (1, 98),
+                                    (15, 9), (10, 10), (47, 0),
+                                    (0, 4)]:
                 for cls1 in [ConstInt, InputArgInt]:
-                    for cls2 in [ConstInt]:#[ConstInt, InputArgInt]:
-                        print 'a_ref:', a_ref
+                    for cls2 in [ConstInt, InputArgInt]:
+                        print 'ptr:', hex(rffi.cast(lltype.Signed, a_ref))
                         print 'a_int:', a_int
                         print 'of:', OF
                         print 'start:', cls1.__name__, start
@@ -5048,6 +5049,9 @@
 
                         scalebox = ConstInt(arraydescr.itemsize)
                         inputargs, oplist = self._get_operation_list(ops,'void')
+                        print("input:", inputargs)
+                        for op in oplist:
+                            print(op)
                         self.execute_operations(inputargs, oplist, 'void')
                         assert len(a) == 100
                         for i in range(100):
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -900,7 +900,7 @@
             self.mc.AGHI(base_loc, ofs_loc)
         else:
             self.mc.AGR(base_loc, ofs_loc)
-        if ofs_loc.is_imm():
+        if startindex_loc.is_imm():
             self.mc.AGHI(base_loc, startindex_loc)
         else:
             self.mc.AGR(base_loc, startindex_loc)
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -157,7 +157,9 @@
         self.temp_boxes.append(box)
         return reg
 
-    def ensure_even_odd_pair(self, var, bind_first=True, must_exist=True, load_loc_odd=True):
+    def ensure_even_odd_pair(self, var, bind_first=True,
+                             must_exist=True, load_loc_odd=True,
+                             move_regs=True):
         self._check_type(var)
         prev_loc = self.loc(var, must_exist=must_exist)
         var2 = TempVar()
@@ -169,7 +171,7 @@
         else:
             loc, loc2 = self.force_allocate_reg_pair(var2, var, self.temp_boxes)
         assert loc.is_even() and loc2.is_odd()
-        if prev_loc is not loc2:
+        if move_regs and prev_loc is not loc2:
             if load_loc_odd:
                 self.assembler.regalloc_mov(prev_loc, loc2)
             else:
@@ -910,12 +912,14 @@
               bind_first=True, must_exist=False, load_loc_odd=False)
         tempvar = TempInt()
         self.rm.temp_boxes.append(tempvar)
-        pad_byte, _ = self.rm.ensure_even_odd_pair(tempvar, bind_first=True, must_exist=False)
+        pad_byte, _ = self.rm.ensure_even_odd_pair(tempvar,
+                              bind_first=True, must_exist=False, move_regs=False)
         startindex_loc = self.ensure_reg_or_16bit_imm(op.getarg(1))
 
         length_box = op.getarg(2)
-        length_loc = self.rm.ensure_reg(length_box, force_in_reg=True,
-                                        selected_reg=length_loc)
+        ll = self.rm.loc(length_box)
+        if length_loc is not ll:
+            self.assembler.regalloc_mov(ll, length_loc)
         ofs_loc = self.ensure_reg_or_16bit_imm(ConstInt(ofs))
         return [base_loc, startindex_loc, length_loc, ofs_loc, imm(itemsize), pad_byte]