[pypy-commit] pypy stmgc-c7: fix

[arigo]

Author: Armin Rigo <arigo at tunes.org>
Branch: stmgc-c7
Changeset: r74513:6371061c0bca
Date: 2014-11-13 23:59 +0100
http://bitbucket.org/pypy/pypy/changeset/6371061c0bca/

Log:	fix

diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -2329,7 +2329,7 @@
                 initial_value = write_locks_base << 4
                 if isinstance(loc_index, RegLoc):
                     if isinstance(loc_base, RegLoc):
-                        mc.MOV_ri(r11, initial_value)
+                        mc.MOV_ri(r11.value, initial_value)
                         mc.ADD_rr(r11.value, loc_base.value)
                         mc.AND_ri(r11.value, ~15)
                     else: