[pypy-commit] pypy stmgc-c4: fix stm_integration_tests and start implementing repeated barriers
Raemi
noreply at buildbot.pypy.org
Tue Oct 22 14:50:58 CEST 2013
Author: Remi Meier <remi.meier at gmail.com>
Branch: stmgc-c4
Changeset: r67513:a347f8e82fa4
Date: 2013-10-22 12:57 +0200
http://bitbucket.org/pypy/pypy/changeset/a347f8e82fa4/
Log: fix stm_integration_tests and start implementing repeated barriers
in assembler
diff --git a/rpython/jit/backend/llsupport/assembler.py b/rpython/jit/backend/llsupport/assembler.py
--- a/rpython/jit/backend/llsupport/assembler.py
+++ b/rpython/jit/backend/llsupport/assembler.py
@@ -81,7 +81,8 @@
self.gc_size_of_header = WORD # for tests
self.memcpy_addr = self.cpu.cast_ptr_to_int(memcpy_fn)
if gc_ll_descr.stm:
- descrs = [gc_ll_descr.P2Rdescr, gc_ll_descr.P2Wdescr]
+ descrs = [gc_ll_descr.A2Rdescr, gc_ll_descr.Q2Rdescr,
+ gc_ll_descr.A2Wdescr, gc_ll_descr.V2Wdescr]
else:
descrs = [gc_ll_descr.write_barrier_descr]
for d in descrs:
diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -189,6 +189,10 @@
return mc.materialize(self.cpu.asmmemmgr, [])
def _build_stm_transaction_break_path(self):
+ assert self.cpu.gc_ll_descr.stm
+ if not we_are_translated():
+ return # tests only
+
""" While arriving on slowpath, we have a gcpattern on stack 0.
This function must preserve all registers
"""
@@ -1357,9 +1361,9 @@
mc.MOV(ebp, mem(ecx, -WORD))
#
if gcrootmap and gcrootmap.is_stm:
- if not hasattr(gc_ll_descr, 'P2Wdescr'):
+ if not hasattr(gc_ll_descr, 'A2Wdescr'):
raise Exception("unreachable code")
- wbdescr = gc_ll_descr.P2Wdescr
+ wbdescr = gc_ll_descr.A2Wdescr
self._stm_barrier_fastpath(mc, wbdescr, [ebp], is_frame=True,
align_stack=align_stack)
return
@@ -2486,43 +2490,48 @@
#
# FASTPATH:
#
- # write_barrier:
+ # A2W:
# (obj->h_revision != stm_private_rev_num)
# || (obj->h_tid & GCFLAG_WRITE_BARRIER) != 0)
- # read_barrier:
+ # V2W:
+ # (obj->h_tid & GCFLAG_WRITE_BARRIER) != 0)
+ # A2R:
# (obj->h_revision != stm_private_rev_num)
# && (FXCACHE_AT(obj) != obj)))
+ # Q2R:
+ # (obj->h_tid & (GCFLAG_PUBLIC_TO_PRIVATE | GCFLAG_MOVED) != 0)
if IS_X86_32: # XXX: todo
todo()
jz_location = 0
jz_location2 = 0
jnz_location = 0
- # compare h_revision with stm_private_rev_num (XXX: may be slow)
- rn = self._get_stm_private_rev_num_addr()
- if we_are_translated():
- # during tests, _get_stm_private_rev_num_addr returns
- # an absolute address, not a tl-offset
- self._tl_segment_if_stm(mc)
- mc.MOV_rj(X86_64_SCRATCH_REG.value, rn)
- else: # testing:
- mc.MOV(X86_64_SCRATCH_REG, heap(rn))
-
- if loc_base == ebp:
- mc.CMP_rb(X86_64_SCRATCH_REG.value, StmGC.H_REVISION)
- else:
- mc.CMP(X86_64_SCRATCH_REG, mem(loc_base, StmGC.H_REVISION))
+ # compare h_revision with stm_private_rev_num
+ if descr.stmcat in ['A2W', 'A2R']:
+ rn = self._get_stm_private_rev_num_addr()
+ if we_are_translated():
+ # during tests, _get_stm_private_rev_num_addr returns
+ # an absolute address, not a tl-offset
+ self._tl_segment_if_stm(mc)
+ mc.MOV_rj(X86_64_SCRATCH_REG.value, rn)
+ else: # testing:
+ mc.MOV(X86_64_SCRATCH_REG, heap(rn))
+
+ if loc_base == ebp:
+ mc.CMP_rb(X86_64_SCRATCH_REG.value, StmGC.H_REVISION)
+ else:
+ mc.CMP(X86_64_SCRATCH_REG, mem(loc_base, StmGC.H_REVISION))
+ #
+ if descr.stmcat == 'A2R':
+ # jump to end if h_rev==priv_rev
+ mc.J_il8(rx86.Conditions['Z'], 0) # patched below
+ jz_location = mc.get_relative_pos()
+ else: # write_barrier
+ # jump to slowpath if h_rev!=priv_rev
+ mc.J_il8(rx86.Conditions['NZ'], 0) # patched below
+ jnz_location = mc.get_relative_pos()
#
- if descr.stmcat == 'P2R':#isinstance(descr, STMReadBarrierDescr):
- # jump to end if h_rev==priv_rev
- mc.J_il8(rx86.Conditions['Z'], 0) # patched below
- jz_location = mc.get_relative_pos()
- else: # write_barrier
- # jump to slowpath if h_rev!=priv_rev
- mc.J_il8(rx86.Conditions['NZ'], 0) # patched below
- jnz_location = mc.get_relative_pos()
-
# FXCACHE_AT(obj) != obj
- if descr.stmcat == 'P2R':#isinstance(descr, STMReadBarrierDescr):
+ if descr.stmcat == 'A2R':
# calculate: temp = obj & FX_MASK
assert StmGC.FX_MASK == 65535
assert not is_frame
@@ -2543,22 +2552,30 @@
mc.CMP_rm(loc_base.value, (X86_64_SCRATCH_REG.value, 0))
mc.J_il8(rx86.Conditions['Z'], 0) # patched below
jz_location2 = mc.get_relative_pos()
+ #
+ # check flags:
+ if descr.stmcat in ['A2W', 'V2W', 'Q2R']:
+ if descr.stmcat in ['A2W', 'V2W']:
+ # obj->h_tid & GCFLAG_WRITE_BARRIER) != 0
+ assert IS_X86_64 and (StmGC.GCFLAG_WRITE_BARRIER >> 32) > 0
+ assert (StmGC.GCFLAG_WRITE_BARRIER >> 40) == 0
+ flags = StmGC.GCFLAG_WRITE_BARRIER >> 32
+ elif descr.stmcat == 'Q2R':
+ # obj->h_tid & PUBLIC_TO_PRIVATE|MOVED
+ flags = StmGC.GCFLAG_PUBLIC_TO_PRIVATE | StmGC.GCFLAG_MOVED
+ assert IS_X86_64 and (flags >> 32) > 0
+ assert (flags >> 40) == 0
+ flags = flags >> 32
- # obj->h_tid & GCFLAG_WRITE_BARRIER) != 0
- if descr.stmcat == 'P2W':#isinstance(descr, STMWriteBarrierDescr):
- assert IS_X86_64 and (StmGC.GCFLAG_WRITE_BARRIER >> 32) > 0
- assert (StmGC.GCFLAG_WRITE_BARRIER >> 40) == 0
off = 4
- flag = StmGC.GCFLAG_WRITE_BARRIER >> 32
if loc_base == ebp:
- mc.TEST8_bi(StmGC.H_TID + off, flag)
+ mc.TEST8_bi(StmGC.H_TID + off, flags)
else:
- mc.TEST8_mi((loc_base.value, StmGC.H_TID + off), flag)
+ mc.TEST8_mi((loc_base.value, StmGC.H_TID + off), flags)
mc.J_il8(rx86.Conditions['Z'], 0) # patched below
jz_location = mc.get_relative_pos()
- # both conditions succeeded, jump to end
-
+ # if flags not set, jump to end
# jump target slowpath:
offset = mc.get_relative_pos() - jnz_location
assert 0 < offset <= 127
@@ -2592,7 +2609,7 @@
offset = mc.get_relative_pos() - jz_location
assert 0 < offset <= 127
mc.overwrite(jz_location - 1, chr(offset))
- if descr.stmcat == 'P2R':#isinstance(descr, STMReadBarrierDescr):
+ if descr.stmcat == 'A2R':#isinstance(descr, STMReadBarrierDescr):
offset = mc.get_relative_pos() - jz_location2
assert 0 < offset <= 127
mc.overwrite(jz_location2 - 1, chr(offset))
diff --git a/rpython/jit/backend/x86/test/test_stm_integration.py b/rpython/jit/backend/x86/test/test_stm_integration.py
--- a/rpython/jit/backend/x86/test/test_stm_integration.py
+++ b/rpython/jit/backend/x86/test/test_stm_integration.py
@@ -152,8 +152,10 @@
self.wb_called_on.append(obj)
return obj
- self.P2Rdescr = FakeSTMBarrier(self, 'P2R', read_barrier)
- self.P2Wdescr = FakeSTMBarrier(self, 'P2W', write_barrier)
+ self.A2Rdescr = FakeSTMBarrier(self, 'A2R', read_barrier)
+ self.Q2Rdescr = FakeSTMBarrier(self, 'Q2R', read_barrier)
+ self.A2Wdescr = FakeSTMBarrier(self, 'A2W', write_barrier)
+ self.V2Wdescr = FakeSTMBarrier(self, 'V2W', write_barrier)
self.do_write_barrier = None
self.get_nursery_top_addr = None
@@ -253,8 +255,10 @@
cpu.__class__)
- self.p2wd = cpu.gc_ll_descr.P2Wdescr
- self.p2rd = cpu.gc_ll_descr.P2Rdescr
+ self.a2wd = cpu.gc_ll_descr.A2Wdescr
+ self.v2wd = cpu.gc_ll_descr.V2Wdescr
+ self.a2rd = cpu.gc_ll_descr.A2Rdescr
+ self.Q2rd = cpu.gc_ll_descr.Q2Rdescr
TP = rffi.CArray(lltype.Signed)
self.priv_rev_num = lltype.malloc(TP, 1, flavor='raw')
@@ -314,7 +318,7 @@
def test_gc_read_barrier_fastpath(self):
from rpython.jit.backend.llsupport.gc import STMReadBarrierDescr
- descr = STMReadBarrierDescr(self.cpu.gc_ll_descr, 'P2R')
+ descr = STMReadBarrierDescr(self.cpu.gc_ll_descr, 'A2R')
called = []
def read(obj):
@@ -356,7 +360,7 @@
def test_gc_write_barrier_fastpath(self):
from rpython.jit.backend.llsupport.gc import STMWriteBarrierDescr
- descr = STMWriteBarrierDescr(self.cpu.gc_ll_descr, 'P2W')
+ descr = STMWriteBarrierDescr(self.cpu.gc_ll_descr, 'A2W')
called = []
def write(obj):
@@ -416,7 +420,7 @@
p0 = BoxPtr()
operations = [
ResOperation(rop.COND_CALL_STM_B, [p0], None,
- descr=self.p2rd),
+ descr=self.a2rd),
ResOperation(rop.FINISH, [p0], None,
descr=BasicFinalDescr(0)),
]
@@ -459,7 +463,7 @@
p0 = BoxPtr()
operations = [
ResOperation(rop.COND_CALL_STM_B, [p0], None,
- descr=self.p2wd),
+ descr=self.a2wd),
ResOperation(rop.FINISH, [p0], None,
descr=BasicFinalDescr(0)),
]
@@ -787,9 +791,9 @@
if llmemory.cast_ptr_to_adr(sgcref) == obj:
return rffi.cast(llmemory.Address, other_sgcref)
return obj
- P2W = FakeSTMBarrier(cpu.gc_ll_descr, 'P2W', write_barrier)
- old_p2w = cpu.gc_ll_descr.P2Wdescr
- cpu.gc_ll_descr.P2Wdescr = P2W
+ A2W = FakeSTMBarrier(cpu.gc_ll_descr, 'A2W', write_barrier)
+ old_a2w = cpu.gc_ll_descr.A2Wdescr
+ cpu.gc_ll_descr.A2Wdescr = A2W
cpu.gc_ll_descr.init_nursery(100)
cpu.setup_once()
@@ -801,10 +805,10 @@
spill.initarglist([p0])
operations = [
ResOperation(rop.COND_CALL_STM_B, [p0], None,
- descr=P2W),
+ descr=A2W),
spill,
ResOperation(rop.COND_CALL_STM_B, [p0], None,
- descr=P2W),
+ descr=A2W),
ResOperation(rop.FINISH, [p0], None,
descr=BasicFinalDescr(0)),
]
@@ -818,7 +822,7 @@
self.assert_in(called_on, [sgcref, other_sgcref])
# for other tests:
- cpu.gc_ll_descr.P2Wdescr = old_p2w
+ cpu.gc_ll_descr.A2Wdescr = old_a2w
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