[pypy-commit] pypy jitframe-on-heap: _store_and_reset_exception

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: jitframe-on-heap
Changeset: r61410:ca4c8057230f
Date: 2013-02-18 16:09 +0100
http://bitbucket.org/pypy/pypy/changeset/ca4c8057230f/

Log:	_store_and_reset_exception

diff --git a/rpython/jit/backend/arm/assembler.py b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -201,23 +201,19 @@
         self.propagate_exception_path = rawstart
 
     def _store_and_reset_exception(self, mc, resloc):
-        assert resloc is r.r0
+        assert resloc is not r.ip
+        tmpreg = r.lr # use lr as a second temporary reg
+        mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value())
+        if resloc is not None: # store
+            self.load_reg(mc, resloc, r.ip, 0)
 
-        self.mc.gen_load_int(resloc.value, self.cpu.pos_exc_value())
-        self.mc.gen_load_int(r.r0.value, self.cpu.pos_exc_value())
-            self.mc.gen_load_int(r.ip.value, 0)
-            self.mc.STR_ri(r.ip.value, r.r0.value)
-        
-        
-            self.mc.LDR_ri(resloc.value, resloc.value)
-            self.mc.MOV(resloc, heap(self.cpu.pos_exc_value()))
+        # reset exception
+        mc.gen_load_int(tmpreg.value, 0)
 
-        with saved_registers(self.mc, [r.r0]):
-            self.mc.gen_load_int(r.r0.value, self.cpu.pos_exc_value())
-            self.mc.gen_load_int(r.ip.value, 0)
-            self.mc.STR_ri(r.ip.value, r.r0.value)
-            self.mc.gen_load_int(r.r0.value, self.cpu.pos_exception())
-            self.mc.STR_ri(r.ip.value, r.r0.value)
+        self.store_reg(mc, tmpreg, r.ip, 0)
+
+        mc.gen_load_int(r.ip.value, self.cpu.pos_exception())
+        self.store_reg(mc, tmpreg, r.ip, 0)
 
     def _build_stack_check_slowpath(self):
         _, _, slowpathaddr = self.cpu.insert_stack_check()
diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -538,12 +538,7 @@
 
         self.mc.CMP_rr(r.ip.value, loc.value)
         self._emit_guard(op, failargs, c.EQ, save_exc=True)
-        self.mc.gen_load_int(loc.value, pos_exc_value.value)
-        if resloc:
-            self.mc.LDR_ri(resloc.value, loc.value)
-        self.mc.MOV_ri(r.ip.value, 0)
-        self.mc.STR_ri(r.ip.value, loc.value)
-        self.mc.STR_ri(r.ip.value, loc1.value)
+        self._store_and_reset_exception(self.mc, resloc)
         return fcond
 
     def emit_op_debug_merge_point(self, op, arglocs, regalloc, fcond):