[pypy-commit] pypy jitframe-on-heap: more work

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: jitframe-on-heap
Changeset: r61263:97b326434c1a
Date: 2013-02-15 15:58 +0200
http://bitbucket.org/pypy/pypy/changeset/97b326434c1a/

Log:	more work

diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -1139,12 +1139,17 @@
         self.mc.STR_ri(tmploc.value, r.ip.value, ofs)
 
     def _call_assembler_load_result(self, op, result_loc):
-        XXX
         if op.result is not None:
             # load the return value from (tmploc, 0)
             kind = op.result.type
+            descr = self.cpu.getarraydescr_for_frame(kind)
             if kind == FLOAT:
-                t = unpack_interiorfielddescr(descrs.as_float)[0]
+                ofs = self.cpu.unpack_arraydescr(descr)
+                assert check_imm_arg(ofs)
+                assert result_loc.is_reg()
+                # we always have a register here, since we have to sync them
+                # before call_assembler
+                self.mc.VLDR(result_loc.value, xxx)
                 if not check_imm_arg(t):
                     self.mc.gen_load_int(r.ip.value, t, cond=fast_path_cond)
                     self.mc.ADD_rr(r.ip.value, r.r0.value, r.ip.value,
diff --git a/rpython/jit/backend/arm/regalloc.py b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -1101,6 +1101,7 @@
     prepare_guard_call_release_gil = prepare_guard_call_may_force
 
     def prepare_guard_call_assembler(self, op, guard_op, fcond):
+        self._prepare_call(op, save_all_regs=True)
         tmploc = self.get_scratch_reg(INT, selected_reg=r.r0)
         locs = self.locs_for_call_assembler(op, guard_op)
         self.possibly_free_vars(guard_op.getfailargs())