[pypy-commit] pypy stmgc-c4: 'base_loc' is not actually ebp, but an immediate, which (on 64-bit) may

[arigo]

Author: Armin Rigo <arigo at tunes.org>
Branch: stmgc-c4
Changeset: r65919:cc9fd4822b91
Date: 2013-08-03 10:37 +0200
http://bitbucket.org/pypy/pypy/changeset/cc9fd4822b91/

Log:	'base_loc' is not actually ebp, but an immediate, which (on 64-bit)
	may not fit a 32-bit number; the encoding Remi did is correct in
	that case. But if it is (or fits) 32-bit, use directly INC_j, with
	the logic of regloc.py to pick.

diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1610,14 +1610,11 @@
         self.load_from_mem(resloc, src_addr, fieldsize_loc, sign_loc)
 
     def genop_discard_increment_debug_counter(self, op, arglocs):
-        assert IS_X86_64
-        # I'm getting lazy. mem_reg_plus_const does not support 
-        # ebp as a register, but that is what we get from the regalloc
-        # (mostly?) -> change to SCRATCH_REG
+        # base_loc and ofs_loc should be immediates, but maybe not
+        # fitting in 32-bit
         base_loc, ofs_loc, size_loc = arglocs
-        self.mc.MOV(X86_64_SCRATCH_REG, base_loc)
-        self.mc.INC_m((X86_64_SCRATCH_REG.value, ofs_loc.getint()))
-    
+        self.mc.INC(addr_add(base_loc, ofs_loc))
+
     def genop_discard_setfield_gc(self, op, arglocs):
         base_loc, ofs_loc, size_loc, value_loc = arglocs
         assert isinstance(size_loc, ImmedLoc)
diff --git a/rpython/jit/backend/x86/regloc.py b/rpython/jit/backend/x86/regloc.py
--- a/rpython/jit/backend/x86/regloc.py
+++ b/rpython/jit/backend/x86/regloc.py
@@ -599,6 +599,7 @@
     TEST8 = _binaryop('TEST8')
     BTS = _binaryop('BTS')
 
+    INC = _unaryop('INC')
     ADD = _binaryop('ADD')
     SUB = _binaryop('SUB')
     IMUL = _binaryop('IMUL')
diff --git a/rpython/jit/backend/x86/rx86.py b/rpython/jit/backend/x86/rx86.py
--- a/rpython/jit/backend/x86/rx86.py
+++ b/rpython/jit/backend/x86/rx86.py
@@ -473,7 +473,8 @@
     # ------------------------------ Arithmetic ------------------------------
 
     INC_m = insn(rex_w, '\xFF', orbyte(0), mem_reg_plus_const(1))
-    
+    INC_j = insn(rex_w, '\xFF', orbyte(0), abs_(1))
+
     ADD_ri,ADD_rr,ADD_rb,_,_,ADD_rm,_,ADD_rj,_,_ = common_modes(0)
     OR_ri, OR_rr, OR_rb, _,_,OR_rm, _,OR_rj, _,_ = common_modes(1)
     AND_ri,AND_rr,AND_rb,_,_,AND_rm,_,AND_rj,_,_ = common_modes(4)