[pypy-commit] pypy ppc-jit-backend: merge
bivab
noreply at buildbot.pypy.org
Tue Feb 7 17:18:00 CET 2012
Author: David Schneider <david.schneider at picle.org>
Branch: ppc-jit-backend
Changeset: r52194:d7c152aca457
Date: 2012-02-07 08:04 -0800
http://bitbucket.org/pypy/pypy/changeset/d7c152aca457/
Log: merge
diff --git a/pypy/jit/backend/detect_cpu.py b/pypy/jit/backend/detect_cpu.py
--- a/pypy/jit/backend/detect_cpu.py
+++ b/pypy/jit/backend/detect_cpu.py
@@ -32,6 +32,7 @@
'x86': 'x86', # Apple
'Power Macintosh': 'ppc',
'ppc64': 'ppc64',
+ 'ppc64_64': 'ppc64',
'x86_64': 'x86',
'amd64': 'x86', # freebsd
'AMD64': 'x86', # win64
@@ -79,6 +80,8 @@
return "pypy.jit.backend.arm.runner", "ArmCPU"
elif backend_name == 'ppc64':
return "pypy.jit.backend.ppc.runner", "PPC_64_CPU"
+ elif backend_name == 'ppc64_64':
+ return "pypy.jit.backend.ppc.runner", "PPC_64_CPU"
else:
raise ProcessorAutodetectError, (
"we have no JIT backend for this cpu: '%s'" % backend_name)
diff --git a/pypy/jit/backend/ppc/ppcgen/_ppcgen.c b/pypy/jit/backend/ppc/_ppcgen.c
rename from pypy/jit/backend/ppc/ppcgen/_ppcgen.c
rename to pypy/jit/backend/ppc/_ppcgen.c
diff --git a/pypy/jit/backend/ppc/ppcgen/arch.py b/pypy/jit/backend/ppc/arch.py
rename from pypy/jit/backend/ppc/ppcgen/arch.py
rename to pypy/jit/backend/ppc/arch.py
--- a/pypy/jit/backend/ppc/ppcgen/arch.py
+++ b/pypy/jit/backend/ppc/arch.py
@@ -1,8 +1,8 @@
# Constants that depend on whether we are on 32-bit or 64-bit
-from pypy.jit.backend.ppc.ppcgen.register import (NONVOLATILES,
- NONVOLATILES_FLOAT,
- MANAGED_REGS)
+from pypy.jit.backend.ppc.register import (NONVOLATILES,
+ NONVOLATILES_FLOAT,
+ MANAGED_REGS)
import sys
if sys.maxint == (2**31 - 1):
diff --git a/pypy/jit/backend/ppc/ppcgen/asmfunc.py b/pypy/jit/backend/ppc/asmfunc.py
rename from pypy/jit/backend/ppc/ppcgen/asmfunc.py
rename to pypy/jit/backend/ppc/asmfunc.py
--- a/pypy/jit/backend/ppc/ppcgen/asmfunc.py
+++ b/pypy/jit/backend/ppc/asmfunc.py
@@ -4,7 +4,7 @@
from pypy.jit.backend.ppc.codebuf import MachineCodeBlockWrapper
from pypy.jit.backend.llsupport.asmmemmgr import AsmMemoryManager
from pypy.rpython.lltypesystem import lltype, rffi
-from pypy.jit.backend.ppc.ppcgen.arch import IS_PPC_32, IS_PPC_64, WORD
+from pypy.jit.backend.ppc.arch import IS_PPC_32, IS_PPC_64, WORD
_ppcgen = None
diff --git a/pypy/jit/backend/ppc/ppcgen/assembler.py b/pypy/jit/backend/ppc/assembler.py
rename from pypy/jit/backend/ppc/ppcgen/assembler.py
rename to pypy/jit/backend/ppc/assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/assembler.py
+++ b/pypy/jit/backend/ppc/assembler.py
@@ -1,5 +1,5 @@
import os
-from pypy.jit.backend.ppc.ppcgen import form
+from pypy.jit.backend.ppc import form
# don't be fooled by the fact that there's some separation between a
# generic assembler class and a PPC assembler class... there's
@@ -62,7 +62,7 @@
def assemble(self, dump=os.environ.has_key('PPY_DEBUG')):
insns = self.assemble0(dump)
- from pypy.jit.backend.ppc.ppcgen import asmfunc
+ from pypy.jit.backend.ppc import asmfunc
c = asmfunc.AsmCode(len(insns)*4)
for i in insns:
c.emit(i)
diff --git a/pypy/jit/backend/ppc/ppcgen/codebuilder.py b/pypy/jit/backend/ppc/codebuilder.py
rename from pypy/jit/backend/ppc/ppcgen/codebuilder.py
rename to pypy/jit/backend/ppc/codebuilder.py
--- a/pypy/jit/backend/ppc/ppcgen/codebuilder.py
+++ b/pypy/jit/backend/ppc/codebuilder.py
@@ -1,16 +1,16 @@
import os
import struct
-from pypy.jit.backend.ppc.ppcgen.ppc_form import PPCForm as Form
-from pypy.jit.backend.ppc.ppcgen.ppc_field import ppc_fields
-from pypy.jit.backend.ppc.ppcgen.regalloc import (TempInt, PPCFrameManager,
+from pypy.jit.backend.ppc.ppc_form import PPCForm as Form
+from pypy.jit.backend.ppc.ppc_field import ppc_fields
+from pypy.jit.backend.ppc.regalloc import (TempInt, PPCFrameManager,
Regalloc)
-from pypy.jit.backend.ppc.ppcgen.assembler import Assembler
-from pypy.jit.backend.ppc.ppcgen.symbol_lookup import lookup
-from pypy.jit.backend.ppc.ppcgen.arch import (IS_PPC_32, WORD, NONVOLATILES,
+from pypy.jit.backend.ppc.assembler import Assembler
+from pypy.jit.backend.ppc.symbol_lookup import lookup
+from pypy.jit.backend.ppc.arch import (IS_PPC_32, WORD, NONVOLATILES,
GPR_SAVE_AREA, IS_PPC_64)
-from pypy.jit.backend.ppc.ppcgen.helper.assembler import gen_emit_cmp_op
-import pypy.jit.backend.ppc.ppcgen.register as r
-import pypy.jit.backend.ppc.ppcgen.condition as c
+from pypy.jit.backend.ppc.helper.assembler import gen_emit_cmp_op
+import pypy.jit.backend.ppc.register as r
+import pypy.jit.backend.ppc.condition as c
from pypy.jit.metainterp.history import (Const, ConstPtr, JitCellToken,
TargetToken, AbstractFailDescr)
from pypy.jit.backend.llsupport.asmmemmgr import (BlockBuilderMixin, AsmMemoryManager, MachineDataBlockWrapper)
diff --git a/pypy/jit/backend/ppc/ppcgen/condition.py b/pypy/jit/backend/ppc/condition.py
rename from pypy/jit/backend/ppc/ppcgen/condition.py
rename to pypy/jit/backend/ppc/condition.py
diff --git a/pypy/jit/backend/ppc/ppcgen/field.py b/pypy/jit/backend/ppc/field.py
rename from pypy/jit/backend/ppc/ppcgen/field.py
rename to pypy/jit/backend/ppc/field.py
diff --git a/pypy/jit/backend/ppc/ppcgen/form.py b/pypy/jit/backend/ppc/form.py
rename from pypy/jit/backend/ppc/ppcgen/form.py
rename to pypy/jit/backend/ppc/form.py
--- a/pypy/jit/backend/ppc/ppcgen/form.py
+++ b/pypy/jit/backend/ppc/form.py
@@ -91,7 +91,7 @@
for fname, v in more_specializatons.iteritems():
field = self.fieldmap[fname]
if field not in self.fields:
- raise FormException, "don't know about '%s' here"%k
+ raise FormException, "don't know about '%s' here" % field
if isinstance(v, str):
ds[field] = self.fieldmap[v]
else:
diff --git a/pypy/jit/backend/ppc/ppcgen/func_builder.py b/pypy/jit/backend/ppc/func_builder.py
rename from pypy/jit/backend/ppc/ppcgen/func_builder.py
rename to pypy/jit/backend/ppc/func_builder.py
--- a/pypy/jit/backend/ppc/ppcgen/func_builder.py
+++ b/pypy/jit/backend/ppc/func_builder.py
@@ -1,6 +1,6 @@
-from pypy.jit.backend.ppc.ppcgen.ppc_assembler import PPCAssembler
-from pypy.jit.backend.ppc.ppcgen.symbol_lookup import lookup
-from pypy.jit.backend.ppc.ppcgen.regname import *
+from pypy.jit.backend.ppc.ppc_assembler import PPCAssembler
+from pypy.jit.backend.ppc.symbol_lookup import lookup
+from pypy.jit.backend.ppc.regname import *
def load_arg(code, argi, typecode):
rD = r3+argi
diff --git a/pypy/jit/backend/ppc/ppcgen/helper/__init__.py b/pypy/jit/backend/ppc/helper/__init__.py
rename from pypy/jit/backend/ppc/ppcgen/helper/__init__.py
rename to pypy/jit/backend/ppc/helper/__init__.py
diff --git a/pypy/jit/backend/ppc/ppcgen/helper/assembler.py b/pypy/jit/backend/ppc/helper/assembler.py
rename from pypy/jit/backend/ppc/ppcgen/helper/assembler.py
rename to pypy/jit/backend/ppc/helper/assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/helper/assembler.py
+++ b/pypy/jit/backend/ppc/helper/assembler.py
@@ -1,10 +1,10 @@
-import pypy.jit.backend.ppc.ppcgen.condition as c
+import pypy.jit.backend.ppc.condition as c
from pypy.rlib.rarithmetic import r_uint, r_longlong, intmask
-from pypy.jit.backend.ppc.ppcgen.arch import (MAX_REG_PARAMS, IS_PPC_32, WORD,
+from pypy.jit.backend.ppc.arch import (MAX_REG_PARAMS, IS_PPC_32, WORD,
BACKCHAIN_SIZE)
from pypy.jit.metainterp.history import FLOAT
from pypy.rlib.unroll import unrolling_iterable
-import pypy.jit.backend.ppc.ppcgen.register as r
+import pypy.jit.backend.ppc.register as r
from pypy.rpython.lltypesystem import rffi, lltype
def gen_emit_cmp_op(condition, signed=True):
diff --git a/pypy/jit/backend/ppc/ppcgen/helper/regalloc.py b/pypy/jit/backend/ppc/helper/regalloc.py
rename from pypy/jit/backend/ppc/ppcgen/helper/regalloc.py
rename to pypy/jit/backend/ppc/helper/regalloc.py
--- a/pypy/jit/backend/ppc/ppcgen/helper/regalloc.py
+++ b/pypy/jit/backend/ppc/helper/regalloc.py
@@ -30,7 +30,7 @@
l0 = self._ensure_value_is_boxed(arg0, forbidden_vars=boxes)
if imm_a1 and not imm_a0:
- l1 = self.make_sure_var_in_reg(arg1, boxes)
+ l1 = self._ensure_value_is_boxed(arg1, boxes)
else:
l1 = self._ensure_value_is_boxed(arg1, forbidden_vars=boxes)
@@ -44,7 +44,7 @@
def f(self, op):
a0 = op.getarg(0)
assert isinstance(a0, Box)
- reg = self.make_sure_var_in_reg(a0)
+ reg = self._ensure_value_is_boxed(a0)
self.possibly_free_vars_for_op(op)
res = self.force_allocate_reg(op.result, [a0])
return [reg, res]
@@ -65,15 +65,8 @@
b0, b1 = boxes
imm_b0 = _check_imm_arg(b0)
imm_b1 = _check_imm_arg(b1)
- if not imm_b0 and imm_b1:
- l0 = self._ensure_value_is_boxed(b0)
- l1 = self.make_sure_var_in_reg(b1, boxes)
- elif imm_b0 and not imm_b1:
- l0 = self.make_sure_var_in_reg(b0)
- l1 = self._ensure_value_is_boxed(b1, boxes)
- else:
- l0 = self._ensure_value_is_boxed(b0)
- l1 = self._ensure_value_is_boxed(b1, boxes)
+ l0 = self._ensure_value_is_boxed(b0, boxes)
+ l1 = self._ensure_value_is_boxed(b1, boxes)
locs = [l0, l1]
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
diff --git a/pypy/jit/backend/ppc/instruction.py b/pypy/jit/backend/ppc/instruction.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/instruction.py
+++ /dev/null
@@ -1,842 +0,0 @@
-r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, \
- r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, \
- r23, r24, r25, r26, r27, r28, r29, r30, r31 = range(32)
-rSCRATCH = r0
-rSP = r1
-rFP = r2 # the ABI doesn't specify a frame pointer. however, we want one
-
-class AllocationSlot(object):
- offset = 0
- number = 0
- def __init__(self):
- # The field alloc points to a singleton used by the register
- # allocator to detect conflicts. No two AllocationSlot
- # instances with the same value in self.alloc can be used at
- # once.
- self.alloc = self
-
- def make_loc(self):
- """ When we assign a variable to one of these registers, we
- call make_loc() to get the actual location instance; that
- instance will have its alloc field set to self. For
- everything but condition registers, this is self."""
- return self
-
-class _StackSlot(AllocationSlot):
- is_register = False
- def __init__(self, offset):
- AllocationSlot.__init__(self)
- self.offset = offset
- def __repr__(self):
- return "stack@%s"%(self.offset,)
-
-_stack_slot_cache = {}
-def stack_slot(offset):
- # because stack slots are put into dictionaries which compare by
- # identity, it is important that there's a unique _StackSlot
- # object for each offset, at least per function generated or
- # something. doing the caching here is easier, though.
- if offset in _stack_slot_cache:
- return _stack_slot_cache[offset]
- _stack_slot_cache[offset] = res = _StackSlot(offset)
- return res
-
-NO_REGISTER = -1
-GP_REGISTER = 0
-FP_REGISTER = 1
-CR_FIELD = 2
-CT_REGISTER = 3
-
-class Register(AllocationSlot):
- is_register = True
- def __init__(self):
- AllocationSlot.__init__(self)
-
-class GPR(Register):
- regclass = GP_REGISTER
- def __init__(self, number):
- Register.__init__(self)
- self.number = number
- def __repr__(self):
- return 'r' + str(self.number)
-gprs = map(GPR, range(32))
-
-class FPR(Register):
- regclass = FP_REGISTER
- def __init__(self, number):
- Register.__init__(self)
- self.number = number
-
-fprs = map(FPR, range(32))
-
-class BaseCRF(Register):
- """ These represent condition registers; however, we never actually
- use these as the location of something in the register allocator.
- Instead, we place it in an instance of CRF which indicates which
- bits are required to extract the value. Note that CRF().alloc will
- always be an instance of this. """
- regclass = CR_FIELD
- def __init__(self, number):
- self.number = number
- self.alloc = self
- def make_loc(self):
- return CRF(self)
-
-crfs = map(BaseCRF, range(8))
-
-class CRF(Register):
- regclass = CR_FIELD
- def __init__(self, crf):
- Register.__init__(self)
- self.alloc = crf
- self.number = crf.number
- self.info = (-1,-1) # (bit, negated)
- def set_info(self, info):
- assert len(info) == 2
- self.info = info
- def make_loc(self):
- # should never call this on a CRF, only a BaseCRF
- raise NotImplementedError
- def move_to_gpr(self, gpr):
- bit, negated = self.info
- return _CRF2GPR(gpr, self.alloc.number*4 + bit, negated)
- def move_from_gpr(self, gpr):
- # cmp2info['ne']
- self.set_info((2, 1))
- return _GPR2CRF(self, gpr)
- def __repr__(self):
- return 'crf' + str(self.number) + str(self.info)
-
-class CTR(Register):
- regclass = CT_REGISTER
- def move_from_gpr(self, gpr):
- return _GPR2CTR(gpr)
-
-ctr = CTR()
-
-_insn_index = [0]
-
-class Insn(object):
- '''
- result is the Var instance that holds the result, or None
- result_regclass is the class of the register the result goes into
-
- reg_args is the vars that need to have registers allocated for them
- reg_arg_regclasses is the type of register that needs to be allocated
- '''
- def __init__(self):
- self._magic_index = _insn_index[0]
- _insn_index[0] += 1
- def __repr__(self):
- return "<%s %d>" % (self.__class__.__name__, self._magic_index)
- def emit(self, asm):
- pass
-
-class Insn_GPR__GPR_GPR(Insn):
- def __init__(self, methptr, result, args):
- Insn.__init__(self)
- self.methptr = methptr
-
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = args
- self.reg_arg_regclasses = [GP_REGISTER, GP_REGISTER]
-
- self.result_reg = None
- self.arg_reg1 = None
- self.arg_reg2 = None
-
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- self.arg_reg1 = allocator.loc_of(self.reg_args[0])
- self.arg_reg2 = allocator.loc_of(self.reg_args[1])
-
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- if self.arg_reg1:
- a1 = "%s@%s"%(self.reg_args[0], self.arg_reg1)
- else:
- a1 = str(self.reg_args[0])
- if self.arg_reg2:
- a2 = "%s@%s"%(self.reg_args[1], self.arg_reg2)
- else:
- a2 = str(self.reg_args[1])
- return "<%s-%s %s %s, %s, %s>" % (self.__class__.__name__, self._magic_index,
- self.methptr.im_func.func_name,
- r, a1, a2)
-
- def emit(self, asm):
- self.methptr(asm,
- self.result_reg.number,
- self.arg_reg1.number,
- self.arg_reg2.number)
-
-class Insn_GPR__GPR_IMM(Insn):
- def __init__(self, methptr, result, args):
- Insn.__init__(self)
- self.methptr = methptr
- self.imm = args[1]
-
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = [args[0]]
- self.reg_arg_regclasses = [GP_REGISTER]
- self.result_reg = None
- self.arg_reg = None
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- self.arg_reg = allocator.loc_of(self.reg_args[0])
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- if self.arg_reg:
- a = "%s@%s"%(self.reg_args[0], self.arg_reg)
- else:
- a = str(self.reg_args[0])
- return "<%s-%d %s %s, %s, (%s)>" % (self.__class__.__name__, self._magic_index,
- self.methptr.im_func.func_name,
- r, a, self.imm.value)
-
- def emit(self, asm):
- self.methptr(asm,
- self.result_reg.number,
- self.arg_reg.number,
- self.imm.value)
-
-class Insn_GPR__GPR(Insn):
- def __init__(self, methptr, result, arg):
- Insn.__init__(self)
- self.methptr = methptr
-
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = [arg]
- self.reg_arg_regclasses = [GP_REGISTER]
-
- self.result_reg = None
- self.arg_reg = None
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- self.arg_reg = allocator.loc_of(self.reg_args[0])
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- if self.arg_reg:
- a = "%s@%s"%(self.reg_args[0], self.arg_reg)
- else:
- a = str(self.reg_args[0])
- return "<%s-%d %s %s, %s>" % (self.__class__.__name__, self._magic_index,
- self.methptr.im_func.func_name, r, a)
- def emit(self, asm):
- self.methptr(asm,
- self.result_reg.number,
- self.arg_reg.number)
-
-
-class Insn_GPR(Insn):
- def __init__(self, methptr, result):
- Insn.__init__(self)
- self.methptr = methptr
-
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result_reg = None
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- return "<%s-%d %s %s>" % (self.__class__.__name__, self._magic_index,
- self.methptr.im_func.func_name, r)
- def emit(self, asm):
- self.methptr(asm,
- self.result_reg.number)
-
-class Insn_GPR__IMM(Insn):
- def __init__(self, methptr, result, args):
- Insn.__init__(self)
- self.methptr = methptr
- self.imm = args[0]
-
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result_reg = None
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- return "<%s-%d %s %s, (%s)>" % (self.__class__.__name__, self._magic_index,
- self.methptr.im_func.func_name, r,
- self.imm.value)
- def emit(self, asm):
- self.methptr(asm,
- self.result_reg.number,
- self.imm.value)
-
-class MoveCRB2GPR(Insn):
- def __init__(self, result, gv_condition):
- Insn.__init__(self)
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = [gv_condition]
- self.reg_arg_regclasses = [CR_FIELD]
- def allocate(self, allocator):
- self.targetreg = allocator.loc_of(self.result)
- self.crf = allocator.loc_of(self.reg_args[0])
- def emit(self, asm):
- assert isinstance(self.crf, CRF)
- bit, negated = self.crf.info
- asm.mfcr(self.targetreg.number)
- asm.extrwi(self.targetreg.number, self.targetreg.number, 1, self.crf.number*4+bit)
- if negated:
- asm.xori(self.targetreg.number, self.targetreg.number, 1)
-
-class Insn_None__GPR_GPR_IMM(Insn):
- def __init__(self, methptr, args):
- Insn.__init__(self)
- self.methptr = methptr
- self.imm = args[2]
-
- self.result = None
- self.result_regclass = NO_REGISTER
- self.reg_args = args[:2]
- self.reg_arg_regclasses = [GP_REGISTER, GP_REGISTER]
- def allocate(self, allocator):
- self.reg1 = allocator.loc_of(self.reg_args[0])
- self.reg2 = allocator.loc_of(self.reg_args[1])
- def __repr__(self):
- return "<%s %s %d>" % (self.__class__.__name__, self.methptr.im_func.func_name, self._magic_index)
-
- def emit(self, asm):
- self.methptr(asm,
- self.reg1.number,
- self.reg2.number,
- self.imm.value)
-
-class Insn_None__GPR_GPR_GPR(Insn):
- def __init__(self, methptr, args):
- Insn.__init__(self)
- self.methptr = methptr
-
- self.result = None
- self.result_regclass = NO_REGISTER
- self.reg_args = args
- self.reg_arg_regclasses = [GP_REGISTER, GP_REGISTER, GP_REGISTER]
- def allocate(self, allocator):
- self.reg1 = allocator.loc_of(self.reg_args[0])
- self.reg2 = allocator.loc_of(self.reg_args[1])
- self.reg3 = allocator.loc_of(self.reg_args[2])
- def __repr__(self):
- return "<%s %s %d>" % (self.__class__.__name__, self.methptr.im_func.func_name, self._magic_index)
-
- def emit(self, asm):
- self.methptr(asm,
- self.reg1.number,
- self.reg2.number,
- self.reg3.number)
-
-class Extrwi(Insn):
- def __init__(self, result, source, size, bit):
- Insn.__init__(self)
-
- self.result = result
- self.result_regclass = GP_REGISTER
- self.reg_args = [source]
- self.reg_arg_regclasses = [GP_REGISTER]
- self.result_reg = None
- self.arg_reg = None
-
- self.size = size
- self.bit = bit
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- self.arg_reg = allocator.loc_of(self.reg_args[0])
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- if self.arg_reg:
- a = "%s@%s"%(self.reg_args[0], self.arg_reg)
- else:
- a = str(self.reg_args[0])
- return "<%s-%d extrwi %s, %s, %s, %s>" % (self.__class__.__name__, self._magic_index,
- r, a, self.size, self.bit)
-
- def emit(self, asm):
- asm.extrwi(self.result_reg.number,
- self.arg_reg.number,
- self.size, self.bit)
-
-
-class CMPInsn(Insn):
- def __init__(self, info, result):
- Insn.__init__(self)
- self.info = info
- self.result = result
- self.result_reg = None
-
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- assert isinstance(self.result_reg, CRF)
- self.result_reg.set_info(self.info)
-
-class CMPW(CMPInsn):
- def __init__(self, info, result, args):
- CMPInsn.__init__(self, info, result)
- self.result_regclass = CR_FIELD
- self.reg_args = args
- self.reg_arg_regclasses = [GP_REGISTER, GP_REGISTER]
- self.arg_reg1 = None
- self.arg_reg2 = None
-
- def allocate(self, allocator):
- CMPInsn.allocate(self, allocator)
- self.arg_reg1 = allocator.loc_of(self.reg_args[0])
- self.arg_reg2 = allocator.loc_of(self.reg_args[1])
-
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- if self.arg_reg1:
- a1 = "%s@%s"%(self.reg_args[0], self.arg_reg1)
- else:
- a1 = str(self.reg_args[0])
- if self.arg_reg2:
- a2 = "%s@%s"%(self.reg_args[1], self.arg_reg2)
- else:
- a2 = str(self.reg_args[1])
- return "<%s-%d %s %s, %s, %s>"%(self.__class__.__name__, self._magic_index,
- self.__class__.__name__.lower(),
- r, a1, a2)
-
- def emit(self, asm):
- asm.cmpw(self.result_reg.number, self.arg_reg1.number, self.arg_reg2.number)
-
-class CMPWL(CMPW):
- def emit(self, asm):
- asm.cmplw(self.result_reg.number, self.arg_reg1.number, self.arg_reg2.number)
-
-class CMPWI(CMPInsn):
- def __init__(self, info, result, args):
- CMPInsn.__init__(self, info, result)
- self.imm = args[1]
- self.result_regclass = CR_FIELD
- self.reg_args = [args[0]]
- self.reg_arg_regclasses = [GP_REGISTER]
- self.arg_reg = None
-
- def allocate(self, allocator):
- CMPInsn.allocate(self, allocator)
- self.arg_reg = allocator.loc_of(self.reg_args[0])
-
- def __repr__(self):
- if self.result_reg:
- r = "%s@%s"%(self.result, self.result_reg)
- else:
- r = str(self.result)
- if self.arg_reg:
- a = "%s@%s"%(self.reg_args[0], self.arg_reg)
- else:
- a = str(self.reg_args[0])
- return "<%s-%d %s %s, %s, (%s)>"%(self.__class__.__name__, self._magic_index,
- self.__class__.__name__.lower(),
- r, a, self.imm.value)
- def emit(self, asm):
- #print "CMPWI", asm.mc.tell()
- asm.cmpwi(self.result_reg.number, self.arg_reg.number, self.imm.value)
-
-class CMPWLI(CMPWI):
- def emit(self, asm):
- asm.cmplwi(self.result_reg.number, self.arg_reg.number, self.imm.value)
-
-
-## class MTCTR(Insn):
-## def __init__(self, result, args):
-## Insn.__init__(self)
-## self.result = result
-## self.result_regclass = CT_REGISTER
-
-## self.reg_args = args
-## self.reg_arg_regclasses = [GP_REGISTER]
-
-## def allocate(self, allocator):
-## self.arg_reg = allocator.loc_of(self.reg_args[0])
-
-## def emit(self, asm):
-## asm.mtctr(self.arg_reg.number)
-
-class Jump(Insn):
- def __init__(self, gv_cond, targetbuilder, jump_if_true, jump_args_gv):
- Insn.__init__(self)
- self.gv_cond = gv_cond
- self.jump_if_true = jump_if_true
-
- self.result = None
- self.result_regclass = NO_REGISTER
- self.reg_args = [gv_cond]
- self.reg_arg_regclasses = [CR_FIELD]
- self.crf = None
-
- self.jump_args_gv = jump_args_gv
- self.targetbuilder = targetbuilder
- def allocate(self, allocator):
- self.crf = allocator.loc_of(self.reg_args[0])
- assert self.crf.info[0] != -1
-
- assert self.targetbuilder.initial_var2loc is None
- self.targetbuilder.initial_var2loc = {}
- from pypy.jit.codegen.ppc.rgenop import Var
- for gv_arg in self.jump_args_gv:
- if isinstance(gv_arg, Var):
- self.targetbuilder.initial_var2loc[gv_arg] = allocator.var2loc[gv_arg]
- allocator.builders_to_tell_spill_offset_to.append(self.targetbuilder)
- def __repr__(self):
- if self.jump_if_true:
- op = 'if_true'
- else:
- op = 'if_false'
- if self.crf:
- a = '%s@%s'%(self.reg_args[0], self.crf)
- else:
- a = self.reg_args[0]
- return '<%s-%d %s %s>'%(self.__class__.__name__, self._magic_index,
- op, a)
- def emit(self, asm):
- if self.targetbuilder.start:
- asm.load_word(rSCRATCH, self.targetbuilder.start)
- else:
- self.targetbuilder.patch_start_here = asm.mc.tell()
- asm.load_word(rSCRATCH, 0)
- asm.mtctr(rSCRATCH)
- bit, negated = self.crf.info
- assert bit != -1
- if negated ^ self.jump_if_true:
- BO = 12 # jump if relavent bit is set in the CR
- else:
- BO = 4 # jump if relavent bit is NOT set in the CR
- asm.bcctr(BO, self.crf.number*4 + bit)
-
-class Label(Insn):
- def __init__(self, label):
- Insn.__init__(self)
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result_regclass = NO_REGISTER
- self.result = None
- self.label = label
- def allocate(self, allocator):
- for gv in self.label.args_gv:
- loc = allocator.loc_of(gv)
- if isinstance(loc, CRF):
- allocator.forget(gv, loc)
- allocator.lru.remove(gv)
- allocator.freeregs[loc.regclass].append(loc.alloc)
- new_loc = allocator._allocate_reg(GP_REGISTER, gv)
- allocator.lru.append(gv)
- allocator.insns.append(loc.move_to_gpr(new_loc.number))
- loc = new_loc
- self.label.arg_locations = []
- for gv in self.label.args_gv:
- loc = allocator.loc_of(gv)
- self.label.arg_locations.append(loc)
- allocator.labels_to_tell_spill_offset_to.append(self.label)
- def __repr__(self):
- if hasattr(self.label, 'arg_locations'):
- arg_locations = '[' + ', '.join(
- ['%s@%s'%(gv, loc) for gv, loc in
- zip(self.label.args_gv, self.label.arg_locations)]) + ']'
- else:
- arg_locations = str(self.label.args_gv)
- return '<Label-%s %s>'%(self._magic_index,
- arg_locations)
- def emit(self, asm):
- self.label.startaddr = asm.mc.tell()
-
-class LoadFramePointer(Insn):
- def __init__(self, result):
- Insn.__init__(self)
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result = result
- self.result_regclass = GP_REGISTER
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- def emit(self, asm):
- asm.mr(self.result_reg.number, rFP)
-
-class CopyIntoStack(Insn):
- def __init__(self, place, v):
- Insn.__init__(self)
- self.reg_args = [v]
- self.reg_arg_regclasses = [GP_REGISTER]
- self.result = None
- self.result_regclass = NO_REGISTER
- self.place = place
- def allocate(self, allocator):
- self.arg_reg = allocator.loc_of(self.reg_args[0])
- self.target_slot = allocator.spill_slot()
- self.place.offset = self.target_slot.offset
- def emit(self, asm):
- asm.stw(self.arg_reg.number, rFP, self.target_slot.offset)
-
-class CopyOffStack(Insn):
- def __init__(self, v, place):
- Insn.__init__(self)
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result = v
- self.result_regclass = GP_REGISTER
- self.place = place
- def allocate(self, allocator):
- self.result_reg = allocator.loc_of(self.result)
- allocator.free_stack_slots.append(stack_slot(self.place.offset))
- def emit(self, asm):
- asm.lwz(self.result_reg.number, rFP, self.place.offset)
-
-class SpillCalleeSaves(Insn):
- def __init__(self):
- Insn.__init__(self)
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result = None
- self.result_regclass = NO_REGISTER
- def allocate(self, allocator):
- # cough cough cough
- callersave = gprs[3:13]
- for v in allocator.var2loc:
- loc = allocator.loc_of(v)
- if loc in callersave:
- allocator.spill(loc, v)
- allocator.freeregs[GP_REGISTER].append(loc)
- def emit(self, asm):
- pass
-
-class LoadArg(Insn):
- def __init__(self, argnumber, arg):
- Insn.__init__(self)
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result = None
- self.result_regclass = NO_REGISTER
-
- self.argnumber = argnumber
- self.arg = arg
- def allocate(self, allocator):
- from pypy.jit.codegen.ppc.rgenop import Var
- if isinstance(self.arg, Var):
- self.loc = allocator.loc_of(self.arg)
- else:
- self.loc = None
- def emit(self, asm):
- if self.argnumber < 8: # magic numbers 'r' us
- targetreg = 3+self.argnumber
- if self.loc is None:
- self.arg.load_now(asm, gprs[targetreg])
- elif self.loc.is_register:
- asm.mr(targetreg, self.loc.number)
- else:
- asm.lwz(targetreg, rFP, self.loc.offset)
- else:
- targetoffset = 24+self.argnumber*4
- if self.loc is None:
- self.arg.load_now(asm, gprs[0])
- asm.stw(r0, r1, targetoffset)
- elif self.loc.is_register:
- asm.stw(self.loc.number, r1, targetoffset)
- else:
- asm.lwz(r0, rFP, self.loc.offset)
- asm.stw(r0, r1, targetoffset)
-
-class CALL(Insn):
- def __init__(self, result, target):
- Insn.__init__(self)
- from pypy.jit.codegen.ppc.rgenop import Var
- if isinstance(target, Var):
- self.reg_args = [target]
- self.reg_arg_regclasses = [CT_REGISTER]
- else:
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.target = target
- self.result = result
- self.result_regclass = GP_REGISTER
- def allocate(self, allocator):
- if self.reg_args:
- assert allocator.loc_of(self.reg_args[0]) is ctr
- self.resultreg = allocator.loc_of(self.result)
- def emit(self, asm):
- if not self.reg_args:
- self.target.load_now(asm, gprs[0])
- asm.mtctr(0)
- asm.bctrl()
- asm.lwz(rFP, rSP, 0)
- if self.resultreg != gprs[3]:
- asm.mr(self.resultreg.number, 3)
-
-
-class AllocTimeInsn(Insn):
- def __init__(self):
- Insn.__init__(self)
- self.reg_args = []
- self.reg_arg_regclasses = []
- self.result_regclass = NO_REGISTER
- self.result = None
-
-class Move(AllocTimeInsn):
- def __init__(self, dest, src):
- AllocTimeInsn.__init__(self)
- self.dest = dest
- self.src = src
- def emit(self, asm):
- asm.mr(self.dest.number, self.src.number)
-
-class Load(AllocTimeInsn):
- def __init__(self, dest, const):
- AllocTimeInsn.__init__(self)
- self.dest = dest
- self.const = const
- def __repr__(self):
- return "<Load-%d %s, (%s)>"%(self._magic_index, self.dest, self.const)
- def emit(self, asm):
- self.const.load_now(asm, self.dest)
-
-class Unspill(AllocTimeInsn):
- """ A special instruction inserted by our register "allocator." It
- indicates that we need to load a value from the stack into a register
- because we spilled a particular value. """
- def __init__(self, var, reg, stack):
- """
- var --- the var we spilled (a Var)
- reg --- the reg we spilled it from (an integer)
- offset --- the offset on the stack we spilled it to (an integer)
- """
- AllocTimeInsn.__init__(self)
- self.var = var
- self.reg = reg
- self.stack = stack
- if not isinstance(self.reg, GPR):
- assert isinstance(self.reg, CRF) or isinstance(self.reg, CTR)
- self.moveinsn = self.reg.move_from_gpr(0)
- else:
- self.moveinsn = None
- def __repr__(self):
- return '<Unspill-%d %s: %s, %s>'%(self._magic_index, self.var, self.reg, self.stack)
- def emit(self, asm):
- if isinstance(self.reg, GPR):
- r = self.reg.number
- else:
- r = 0
- asm.lwz(r, rFP, self.stack.offset)
- if self.moveinsn:
- self.moveinsn.emit(asm)
-
-class Spill(AllocTimeInsn):
- """ A special instruction inserted by our register "allocator."
- It indicates that we need to store a value from the register into
- the stack because we spilled a particular value."""
- def __init__(self, var, reg, stack):
- """
- var --- the var we are spilling (a Var)
- reg --- the reg we are spilling it from (an integer)
- offset --- the offset on the stack we are spilling it to (an integer)
- """
- AllocTimeInsn.__init__(self)
- self.var = var
- self.reg = reg
- self.stack = stack
- def __repr__(self):
- return '<Spill-%d %s: %s, %s>'%(self._magic_index, self.var, self.stack, self.reg)
- def emit(self, asm):
- if isinstance(self.reg, GPR):
- r = self.reg.number
- else:
- assert isinstance(self.reg, CRF)
- self.reg.move_to_gpr(0).emit(asm)
- r = 0
- #print 'spilling to', self.stack.offset
- asm.stw(r, rFP, self.stack.offset)
-
-class _CRF2GPR(AllocTimeInsn):
- def __init__(self, targetreg, bit, negated):
- AllocTimeInsn.__init__(self)
- self.targetreg = targetreg
- self.bit = bit
- self.negated = negated
- def __repr__(self):
- number = self.bit // 4
- bit = self.bit % 4
- return '<CRF2GPR-%d r%s, crf%s(%s, %s)>' % (
- self._magic_index, self.targetreg, number, bit, self.negated)
- def emit(self, asm):
- asm.mfcr(self.targetreg)
- asm.extrwi(self.targetreg, self.targetreg, 1, self.bit)
- if self.negated:
- asm.xori(self.targetreg, self.targetreg, 1)
-
-class _GPR2CRF(AllocTimeInsn):
- def __init__(self, targetreg, fromreg):
- AllocTimeInsn.__init__(self)
- self.targetreg = targetreg
- self.fromreg = fromreg
- def __repr__(self):
- return '<GPR2CRF-%d %s, r%s>' % (
- self._magic_index, self.targetreg, self.fromreg)
- def emit(self, asm):
- asm.cmpwi(self.targetreg.number, self.fromreg, 0)
-
-class _GPR2CTR(AllocTimeInsn):
- def __init__(self, fromreg):
- AllocTimeInsn.__init__(self)
- self.fromreg = fromreg
- def emit(self, asm):
- asm.mtctr(self.fromreg)
-
-class Return(Insn):
- """ Ensures the return value is in r3 """
- def __init__(self, var):
- Insn.__init__(self)
- self.var = var
- self.reg_args = [self.var]
- self.reg_arg_regclasses = [GP_REGISTER]
- self.result = None
- self.result_regclass = NO_REGISTER
- self.reg = None
- def allocate(self, allocator):
- self.reg = allocator.loc_of(self.reg_args[0])
- def emit(self, asm):
- if self.reg.number != 3:
- asm.mr(r3, self.reg.number)
-
-class FakeUse(Insn):
- """ A fake use of a var to get it into a register. And reserving
- a condition register field."""
- def __init__(self, rvar, var):
- Insn.__init__(self)
- self.var = var
- self.reg_args = [self.var]
- self.reg_arg_regclasses = [GP_REGISTER]
- self.result = rvar
- self.result_regclass = CR_FIELD
- def allocate(self, allocator):
- pass
- def emit(self, asm):
- pass
diff --git a/pypy/jit/backend/ppc/ppcgen/jump.py b/pypy/jit/backend/ppc/jump.py
rename from pypy/jit/backend/ppc/ppcgen/jump.py
rename to pypy/jit/backend/ppc/jump.py
--- a/pypy/jit/backend/ppc/ppcgen/jump.py
+++ b/pypy/jit/backend/ppc/jump.py
@@ -76,7 +76,7 @@
src_locations2, dst_locations2, tmpreg2):
# find and push the xmm stack locations from src_locations2 that
# are going to be overwritten by dst_locations1
- from pypy.jit.backend.ppc.ppcgen.arch import WORD
+ from pypy.jit.backend.ppc.arch import WORD
extrapushes = []
dst_keys = {}
for loc in dst_locations1:
diff --git a/pypy/jit/backend/ppc/ppcgen/locations.py b/pypy/jit/backend/ppc/locations.py
rename from pypy/jit/backend/ppc/ppcgen/locations.py
rename to pypy/jit/backend/ppc/locations.py
diff --git a/pypy/jit/backend/ppc/ppcgen/opassembler.py b/pypy/jit/backend/ppc/opassembler.py
rename from pypy/jit/backend/ppc/ppcgen/opassembler.py
rename to pypy/jit/backend/ppc/opassembler.py
--- a/pypy/jit/backend/ppc/ppcgen/opassembler.py
+++ b/pypy/jit/backend/ppc/opassembler.py
@@ -1,19 +1,19 @@
-from pypy.jit.backend.ppc.ppcgen.helper.assembler import (gen_emit_cmp_op,
+from pypy.jit.backend.ppc.helper.assembler import (gen_emit_cmp_op,
gen_emit_unary_cmp_op)
-import pypy.jit.backend.ppc.ppcgen.condition as c
-import pypy.jit.backend.ppc.ppcgen.register as r
-from pypy.jit.backend.ppc.ppcgen.arch import (IS_PPC_32, WORD,
+import pypy.jit.backend.ppc.condition as c
+import pypy.jit.backend.ppc.register as r
+from pypy.jit.backend.ppc.arch import (IS_PPC_32, WORD,
GPR_SAVE_AREA, BACKCHAIN_SIZE,
MAX_REG_PARAMS)
from pypy.jit.metainterp.history import (JitCellToken, TargetToken, Box,
AbstractFailDescr, FLOAT, INT, REF)
from pypy.rlib.objectmodel import we_are_translated
-from pypy.jit.backend.ppc.ppcgen.helper.assembler import (count_reg_args,
+from pypy.jit.backend.ppc.helper.assembler import (count_reg_args,
Saved_Volatiles)
-from pypy.jit.backend.ppc.ppcgen.jump import remap_frame_layout
-from pypy.jit.backend.ppc.ppcgen.codebuilder import OverwritingBuilder
-from pypy.jit.backend.ppc.ppcgen.regalloc import TempPtr, TempInt
+from pypy.jit.backend.ppc.jump import remap_frame_layout
+from pypy.jit.backend.ppc.codebuilder import OverwritingBuilder
+from pypy.jit.backend.ppc.regalloc import TempPtr, TempInt
from pypy.jit.backend.llsupport import symbolic
from pypy.rpython.lltypesystem import rstr, rffi, lltype
from pypy.jit.metainterp.resoperation import rop
@@ -854,24 +854,6 @@
self.emit_call(op, arglocs, regalloc)
self.propagate_memoryerror_if_r3_is_null()
- # from: ../x86/regalloc.py:750
- # called from regalloc
- # XXX kill this function at some point
- def _regalloc_malloc_varsize(self, size, size_box, vloc, vbox,
- ofs_items_loc, regalloc, result):
- if IS_PPC_32:
- self.mc.mullw(size.value, size.value, vloc.value)
- else:
- self.mc.mulld(size.value, size.value, vloc.value)
- if ofs_items_loc.is_imm():
- self.mc.addi(size.value, size.value, ofs_items_loc.value)
- else:
- self.mc.add(size.value, size.value, ofs_items_loc.value)
- force_index = self.write_new_force_index()
- regalloc.force_spill_var(vbox)
- self._emit_call(force_index, self.malloc_func_addr, [size_box], regalloc,
- result=result)
-
def set_vtable(self, box, vtable):
if self.cpu.vtable_offset is not None:
adr = rffi.cast(lltype.Signed, vtable)
diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py b/pypy/jit/backend/ppc/ppc_assembler.py
rename from pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
rename to pypy/jit/backend/ppc/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppc_assembler.py
@@ -1,27 +1,27 @@
import os
import struct
-from pypy.jit.backend.ppc.ppcgen.ppc_form import PPCForm as Form
-from pypy.jit.backend.ppc.ppcgen.ppc_field import ppc_fields
-from pypy.jit.backend.ppc.ppcgen.regalloc import (TempInt, PPCFrameManager,
- Regalloc)
-from pypy.jit.backend.ppc.ppcgen.assembler import Assembler
-from pypy.jit.backend.ppc.ppcgen.opassembler import OpAssembler
-from pypy.jit.backend.ppc.ppcgen.symbol_lookup import lookup
-from pypy.jit.backend.ppc.ppcgen.codebuilder import PPCBuilder
-from pypy.jit.backend.ppc.ppcgen.jump import remap_frame_layout
-from pypy.jit.backend.ppc.ppcgen.arch import (IS_PPC_32, IS_PPC_64, WORD,
- NONVOLATILES, MAX_REG_PARAMS,
- GPR_SAVE_AREA, BACKCHAIN_SIZE,
- FPR_SAVE_AREA,
- FLOAT_INT_CONVERSION, FORCE_INDEX,
- SIZE_LOAD_IMM_PATCH_SP)
-from pypy.jit.backend.ppc.ppcgen.helper.assembler import (gen_emit_cmp_op,
- encode32, encode64,
- decode32, decode64,
- count_reg_args,
- Saved_Volatiles)
-import pypy.jit.backend.ppc.ppcgen.register as r
-import pypy.jit.backend.ppc.ppcgen.condition as c
+from pypy.jit.backend.ppc.ppc_form import PPCForm as Form
+from pypy.jit.backend.ppc.ppc_field import ppc_fields
+from pypy.jit.backend.ppc.regalloc import (TempInt, PPCFrameManager,
+ Regalloc)
+from pypy.jit.backend.ppc.assembler import Assembler
+from pypy.jit.backend.ppc.opassembler import OpAssembler
+from pypy.jit.backend.ppc.symbol_lookup import lookup
+from pypy.jit.backend.ppc.codebuilder import PPCBuilder
+from pypy.jit.backend.ppc.jump import remap_frame_layout
+from pypy.jit.backend.ppc.arch import (IS_PPC_32, IS_PPC_64, WORD,
+ NONVOLATILES, MAX_REG_PARAMS,
+ GPR_SAVE_AREA, BACKCHAIN_SIZE,
+ FPR_SAVE_AREA,
+ FLOAT_INT_CONVERSION, FORCE_INDEX,
+ SIZE_LOAD_IMM_PATCH_SP)
+from pypy.jit.backend.ppc.helper.assembler import (gen_emit_cmp_op,
+ encode32, encode64,
+ decode32, decode64,
+ count_reg_args,
+ Saved_Volatiles)
+import pypy.jit.backend.ppc.register as r
+import pypy.jit.backend.ppc.condition as c
from pypy.jit.metainterp.history import (Const, ConstPtr, JitCellToken,
TargetToken, AbstractFailDescr)
from pypy.jit.backend.llsupport.asmmemmgr import (BlockBuilderMixin,
@@ -40,7 +40,7 @@
from pypy.rpython.annlowlevel import llhelper
from pypy.rlib.objectmodel import we_are_translated
from pypy.rpython.lltypesystem.lloperation import llop
-from pypy.jit.backend.ppc.ppcgen.locations import StackLocation, get_spp_offset
+from pypy.jit.backend.ppc.locations import StackLocation, get_spp_offset
memcpy_fn = rffi.llexternal('memcpy', [llmemory.Address, llmemory.Address,
rffi.SIZE_T], lltype.Void,
diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_field.py b/pypy/jit/backend/ppc/ppc_field.py
rename from pypy/jit/backend/ppc/ppcgen/ppc_field.py
rename to pypy/jit/backend/ppc/ppc_field.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_field.py
+++ b/pypy/jit/backend/ppc/ppc_field.py
@@ -1,5 +1,5 @@
-from pypy.jit.backend.ppc.ppcgen.field import Field
-from pypy.jit.backend.ppc.ppcgen import regname
+from pypy.jit.backend.ppc.field import Field
+from pypy.jit.backend.ppc import regname
fields = { # bit margins are *inclusive*! (and bit 0 is
# most-significant, 31 least significant)
diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_form.py b/pypy/jit/backend/ppc/ppc_form.py
rename from pypy/jit/backend/ppc/ppcgen/ppc_form.py
rename to pypy/jit/backend/ppc/ppc_form.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_form.py
+++ b/pypy/jit/backend/ppc/ppc_form.py
@@ -1,5 +1,5 @@
-from pypy.jit.backend.ppc.ppcgen.form import Form
-from pypy.jit.backend.ppc.ppcgen.ppc_field import ppc_fields
+from pypy.jit.backend.ppc.form import Form
+from pypy.jit.backend.ppc.ppc_field import ppc_fields
class PPCForm(Form):
fieldmap = ppc_fields
diff --git a/pypy/jit/backend/ppc/ppcgen/__init__.py b/pypy/jit/backend/ppc/ppcgen/__init__.py
deleted file mode 100644
diff --git a/pypy/jit/backend/ppc/ppcgen/autopath.py b/pypy/jit/backend/ppc/ppcgen/autopath.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/ppcgen/autopath.py
+++ /dev/null
@@ -1,114 +0,0 @@
-"""
-self cloning, automatic path configuration
-
-copy this into any subdirectory of pypy from which scripts need
-to be run, typically all of the test subdirs.
-The idea is that any such script simply issues
-
- import autopath
-
-and this will make sure that the parent directory containing "pypy"
-is in sys.path.
-
-If you modify the master "autopath.py" version (in pypy/tool/autopath.py)
-you can directly run it which will copy itself on all autopath.py files
-it finds under the pypy root directory.
-
-This module always provides these attributes:
-
- pypydir pypy root directory path
- this_dir directory where this autopath.py resides
-
-"""
-
-
-def __dirinfo(part):
- """ return (partdir, this_dir) and insert parent of partdir
- into sys.path. If the parent directories don't have the part
- an EnvironmentError is raised."""
-
- import sys, os
- try:
- head = this_dir = os.path.realpath(os.path.dirname(__file__))
- except NameError:
- head = this_dir = os.path.realpath(os.path.dirname(sys.argv[0]))
-
- while head:
- partdir = head
- head, tail = os.path.split(head)
- if tail == part:
- break
- else:
- raise EnvironmentError, "'%s' missing in '%r'" % (partdir, this_dir)
-
- pypy_root = os.path.join(head, '')
- try:
- sys.path.remove(head)
- except ValueError:
- pass
- sys.path.insert(0, head)
-
- munged = {}
- for name, mod in sys.modules.items():
- if '.' in name:
- continue
- fn = getattr(mod, '__file__', None)
- if not isinstance(fn, str):
- continue
- newname = os.path.splitext(os.path.basename(fn))[0]
- if not newname.startswith(part + '.'):
- continue
- path = os.path.join(os.path.dirname(os.path.realpath(fn)), '')
- if path.startswith(pypy_root) and newname != part:
- modpaths = os.path.normpath(path[len(pypy_root):]).split(os.sep)
- if newname != '__init__':
- modpaths.append(newname)
- modpath = '.'.join(modpaths)
- if modpath not in sys.modules:
- munged[modpath] = mod
-
- for name, mod in munged.iteritems():
- if name not in sys.modules:
- sys.modules[name] = mod
- if '.' in name:
- prename = name[:name.rfind('.')]
- postname = name[len(prename)+1:]
- if prename not in sys.modules:
- __import__(prename)
- if not hasattr(sys.modules[prename], postname):
- setattr(sys.modules[prename], postname, mod)
-
- return partdir, this_dir
-
-def __clone():
- """ clone master version of autopath.py into all subdirs """
- from os.path import join, walk
- if not this_dir.endswith(join('pypy','tool')):
- raise EnvironmentError("can only clone master version "
- "'%s'" % join(pypydir, 'tool',_myname))
-
-
- def sync_walker(arg, dirname, fnames):
- if _myname in fnames:
- fn = join(dirname, _myname)
- f = open(fn, 'rwb+')
- try:
- if f.read() == arg:
- print "checkok", fn
- else:
- print "syncing", fn
- f = open(fn, 'w')
- f.write(arg)
- finally:
- f.close()
- s = open(join(pypydir, 'tool', _myname), 'rb').read()
- walk(pypydir, sync_walker, s)
-
-_myname = 'autopath.py'
-
-# set guaranteed attributes
-
-pypydir, this_dir = __dirinfo('pypy')
-
-if __name__ == '__main__':
- __clone()
diff --git a/pypy/jit/backend/ppc/ppcgen/pystructs.py b/pypy/jit/backend/ppc/ppcgen/pystructs.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/ppcgen/pystructs.py
+++ /dev/null
@@ -1,22 +0,0 @@
-class PyVarObject(object):
- ob_size = 8
-
-class PyObject(object):
- ob_refcnt = 0
- ob_type = 4
-
-class PyTupleObject(object):
- ob_item = 12
-
-class PyTypeObject(object):
- tp_name = 12
- tp_basicsize = 16
- tp_itemsize = 20
- tp_dealloc = 24
-
-class PyFloatObject(object):
- ob_fval = 8
-
-class PyIntObject(object):
- ob_ival = 8
-
diff --git a/pypy/jit/backend/ppc/ppcgen/rassemblermaker.py b/pypy/jit/backend/ppc/ppcgen/rassemblermaker.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/ppcgen/rassemblermaker.py
+++ /dev/null
@@ -1,63 +0,0 @@
-from pypy.tool.sourcetools import compile2
-from pypy.rlib.rarithmetic import r_uint
-from pypy.jit.backend.ppc.ppcgen.form import IDesc, IDupDesc
-
-## "opcode": ( 0, 5),
-## "rA": (11, 15, 'unsigned', regname._R),
-## "rB": (16, 20, 'unsigned', regname._R),
-## "Rc": (31, 31),
-## "rD": ( 6, 10, 'unsigned', regname._R),
-## "OE": (21, 21),
-## "XO2": (22, 30),
-
-## XO = Form("rD", "rA", "rB", "OE", "XO2", "Rc")
-
-## add = XO(31, XO2=266, OE=0, Rc=0)
-
-## def add(rD, rA, rB):
-## v = 0
-## v |= (31&(2**(5-0+1)-1)) << (32-5-1)
-## ...
-## return v
-
-def make_func(name, desc):
- sig = []
- fieldvalues = []
- for field in desc.fields:
- if field in desc.specializations:
- fieldvalues.append((field, desc.specializations[field]))
- else:
- sig.append(field.name)
- fieldvalues.append((field, field.name))
- if isinstance(desc, IDupDesc):
- for destfield, srcfield in desc.dupfields.iteritems():
- fieldvalues.append((destfield, srcfield.name))
- body = ['v = r_uint(0)']
- assert 'v' not in sig # that wouldn't be funny
- #body.append('print %r'%name + ', ' + ', '.join(["'%s:', %s"%(s, s) for s in sig]))
- for field, value in fieldvalues:
- if field.name == 'spr':
- body.append('spr = (%s&31) << 5 | (%s >> 5 & 31)'%(value, value))
- value = 'spr'
- body.append('v |= (%3s & r_uint(%#05x)) << %d'%(value,
- field.mask,
- (32 - field.right - 1)))
- body.append('self.emit(v)')
- src = 'def %s(self, %s):\n %s'%(name, ', '.join(sig), '\n '.join(body))
- d = {'r_uint':r_uint}
- #print src
- exec compile2(src) in d
- return d[name]
-
-def make_rassembler(cls):
- bases = [make_rassembler(b) for b in cls.__bases__]
- ns = {}
- for k, v in cls.__dict__.iteritems():
- if isinstance(v, IDesc):
- v = make_func(k, v)
- ns[k] = v
- rcls = type('R' + cls.__name__, tuple(bases), ns)
- def emit(self, value):
- self.insts.append(value)
- rcls.emit = emit
- return rcls
diff --git a/pypy/jit/backend/ppc/ppcgen/regalloc.py b/pypy/jit/backend/ppc/ppcgen/regalloc.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/ppcgen/regalloc.py
+++ /dev/null
@@ -1,989 +0,0 @@
-from pypy.jit.backend.llsupport.regalloc import (RegisterManager, FrameManager,
- TempBox, compute_vars_longevity)
-from pypy.jit.backend.ppc.ppcgen.arch import (WORD, MY_COPY_OF_REGS)
-from pypy.jit.backend.ppc.ppcgen.jump import (remap_frame_layout_mixed,
- remap_frame_layout)
-from pypy.jit.backend.ppc.ppcgen.locations import imm
-from pypy.jit.backend.ppc.ppcgen.helper.regalloc import (_check_imm_arg,
- check_imm_box,
- prepare_cmp_op,
- prepare_unary_int_op,
- prepare_binary_int_op,
- prepare_binary_int_op_with_imm,
- prepare_unary_cmp)
-from pypy.jit.metainterp.history import (INT, REF, FLOAT, Const, ConstInt,
- ConstPtr, Box)
-from pypy.jit.metainterp.history import JitCellToken, TargetToken
-from pypy.jit.metainterp.resoperation import rop
-from pypy.jit.backend.ppc.ppcgen import locations
-from pypy.rpython.lltypesystem import rffi, lltype, rstr
-from pypy.jit.backend.llsupport import symbolic
-from pypy.jit.backend.llsupport.descr import ArrayDescr
-from pypy.jit.codewriter.effectinfo import EffectInfo
-import pypy.jit.backend.ppc.ppcgen.register as r
-from pypy.jit.codewriter import heaptracker
-from pypy.jit.backend.llsupport.descr import unpack_arraydescr
-from pypy.jit.backend.llsupport.descr import unpack_fielddescr
-from pypy.jit.backend.llsupport.descr import unpack_interiorfielddescr
-
-# xxx hack: set a default value for TargetToken._arm_loop_code. If 0, we know
-# that it is a LABEL that was not compiled yet.
-TargetToken._ppc_loop_code = 0
-
-class TempInt(TempBox):
- type = INT
-
- def __repr__(self):
- return "<TempInt at %s>" % (id(self),)
-
-class TempPtr(TempBox):
- type = REF
-
- def __repr__(self):
- return "<TempPtr at %s>" % (id(self),)
-
-class PPCRegisterManager(RegisterManager):
- all_regs = r.MANAGED_REGS
- box_types = None # or a list of acceptable types
- no_lower_byte_regs = all_regs
- save_around_call_regs = r.VOLATILES
-
- REGLOC_TO_COPY_AREA_OFS = {
- r.r0: MY_COPY_OF_REGS + 0 * WORD,
- r.r2: MY_COPY_OF_REGS + 1 * WORD,
- r.r3: MY_COPY_OF_REGS + 2 * WORD,
- r.r4: MY_COPY_OF_REGS + 3 * WORD,
- r.r5: MY_COPY_OF_REGS + 4 * WORD,
- r.r6: MY_COPY_OF_REGS + 5 * WORD,
- r.r7: MY_COPY_OF_REGS + 6 * WORD,
- r.r8: MY_COPY_OF_REGS + 7 * WORD,
- r.r9: MY_COPY_OF_REGS + 8 * WORD,
- r.r10: MY_COPY_OF_REGS + 9 * WORD,
- r.r11: MY_COPY_OF_REGS + 10 * WORD,
- r.r12: MY_COPY_OF_REGS + 11 * WORD,
- r.r13: MY_COPY_OF_REGS + 12 * WORD,
- r.r14: MY_COPY_OF_REGS + 13 * WORD,
- r.r15: MY_COPY_OF_REGS + 14 * WORD,
- r.r16: MY_COPY_OF_REGS + 15 * WORD,
- r.r17: MY_COPY_OF_REGS + 16 * WORD,
- r.r18: MY_COPY_OF_REGS + 17 * WORD,
- r.r19: MY_COPY_OF_REGS + 18 * WORD,
- r.r20: MY_COPY_OF_REGS + 19 * WORD,
- r.r21: MY_COPY_OF_REGS + 20 * WORD,
- r.r22: MY_COPY_OF_REGS + 21 * WORD,
- r.r23: MY_COPY_OF_REGS + 22 * WORD,
- r.r24: MY_COPY_OF_REGS + 23 * WORD,
- r.r25: MY_COPY_OF_REGS + 24 * WORD,
- r.r26: MY_COPY_OF_REGS + 25 * WORD,
- r.r27: MY_COPY_OF_REGS + 26 * WORD,
- r.r28: MY_COPY_OF_REGS + 27 * WORD,
- r.r29: MY_COPY_OF_REGS + 28 * WORD,
- r.r30: MY_COPY_OF_REGS + 29 * WORD,
- r.r31: MY_COPY_OF_REGS + 30 * WORD,
- }
-
- def __init__(self, longevity, frame_manager=None, assembler=None):
- RegisterManager.__init__(self, longevity, frame_manager, assembler)
-
- def call_result_location(self, v):
- return r.r3
-
- def convert_to_imm(self, c):
- if isinstance(c, ConstInt):
- val = rffi.cast(lltype.Signed, c.value)
- return locations.ImmLocation(val)
- else:
- assert isinstance(c, ConstPtr)
- return locations.ImmLocation(rffi.cast(lltype.Signed, c.value))
-
- def ensure_value_is_boxed(self, thing, forbidden_vars=None):
- loc = None
- if isinstance(thing, Const):
- if isinstance(thing, ConstPtr):
- tp = REF
- else:
- tp = INT
- loc = self.get_scratch_reg(tp, forbidden_vars=self.temp_boxes
- + forbidden_vars)
- immvalue = self.convert_to_imm(thing)
- self.assembler.load(loc, immvalue)
- else:
- loc = self.make_sure_var_in_reg(thing,
- forbidden_vars=forbidden_vars)
- return loc
-
- def allocate_scratch_reg(self, type=INT, selected_reg=None, forbidden_vars=None):
- """Allocate a scratch register, possibly spilling a managed register.
- This register is freed after emitting the current operation and can not
- be spilled"""
- box = TempBox()
- reg = self.force_allocate_reg(box,
- selected_reg=selected_reg,
- forbidden_vars=forbidden_vars)
- return reg, box
-
- def get_scratch_reg(self, type=INT, forbidden_vars=[], selected_reg=None):
- assert type == INT or type == REF
- box = TempBox()
- self.temp_boxes.append(box)
- reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
- selected_reg=selected_reg)
- return reg
-
-class PPCFrameManager(FrameManager):
- def __init__(self):
- FrameManager.__init__(self)
- self.used = []
-
- @staticmethod
- def frame_pos(loc, type):
- num_words = PPCFrameManager.frame_size(type)
- if type == FLOAT:
- assert 0, "not implemented yet"
- return locations.StackLocation(loc, num_words=num_words, type=type)
-
- @staticmethod
- def frame_size(type):
- if type == FLOAT:
- assert 0, "TODO"
- return 1
-
- @staticmethod
- def get_loc_index(loc):
- assert loc.is_stack()
- if loc.type == FLOAT:
- assert 0, "not implemented yet"
- return loc.position
-
-class Regalloc(object):
-
- def __init__(self, frame_manager=None, assembler=None):
- self.cpu = assembler.cpu
- self.frame_manager = frame_manager
- self.assembler = assembler
- self.jump_target_descr = None
- self.final_jump_op = None
-
- def _prepare(self, inputargs, operations):
- longevity, last_real_usage = compute_vars_longevity(
- inputargs, operations)
- self.longevity = longevity
- self.last_real_usage = last_real_usage
- fm = self.frame_manager
- asm = self.assembler
- self.rm = PPCRegisterManager(longevity, fm, asm)
-
- def prepare_loop(self, inputargs, operations):
- self._prepare(inputargs, operations)
- self._set_initial_bindings(inputargs)
- self.possibly_free_vars(list(inputargs))
-
- def prepare_bridge(self, inputargs, arglocs, ops):
- self._prepare(inputargs, ops)
- self._update_bindings(arglocs, inputargs)
-
- def _set_initial_bindings(self, inputargs):
- arg_index = 0
- count = 0
- n_register_args = len(r.PARAM_REGS)
- cur_frame_pos = -self.assembler.OFFSET_STACK_ARGS // WORD
- for box in inputargs:
- assert isinstance(box, Box)
- # handle inputargs in argument registers
- if box.type == FLOAT and arg_index % 2 != 0:
- assert 0, "not implemented yet"
- if arg_index < n_register_args:
- if box.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- loc = r.PARAM_REGS[arg_index]
- self.try_allocate_reg(box, selected_reg=loc)
- arg_index += 1
- else:
- # treat stack args as stack locations with a negative offset
- if box.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- cur_frame_pos -= 1
- count += 1
- loc = self.frame_manager.frame_pos(cur_frame_pos, box.type)
- self.frame_manager.set_binding(box, loc)
-
- def _update_bindings(self, locs, inputargs):
- used = {}
- i = 0
- for loc in locs:
- arg = inputargs[i]
- i += 1
- if loc.is_reg():
- self.rm.reg_bindings[arg] = loc
- elif loc.is_vfp_reg():
- assert 0, "not supported"
- else:
- assert loc.is_stack()
- self.frame_manager.set_binding(arg, loc)
- used[loc] = None
-
- # XXX combine with x86 code and move to llsupport
- self.rm.free_regs = []
- for reg in self.rm.all_regs:
- if reg not in used:
- self.rm.free_regs.append(reg)
- # note: we need to make a copy of inputargs because possibly_free_vars
- # is also used on op args, which is a non-resizable list
- self.possibly_free_vars(list(inputargs))
-
- def possibly_free_var(self, var):
- self.rm.possibly_free_var(var)
-
- def possibly_free_vars(self, vars):
- for var in vars:
- self.possibly_free_var(var)
-
- def possibly_free_vars_for_op(self, op):
- for i in range(op.numargs()):
- var = op.getarg(i)
- if var is not None:
- self.possibly_free_var(var)
-
- def try_allocate_reg(self, v, selected_reg=None, need_lower_byte=False):
- return self.rm.try_allocate_reg(v, selected_reg, need_lower_byte)
-
- def force_allocate_reg(self, var, forbidden_vars=[], selected_reg=None,
- need_lower_byte=False):
- return self.rm.force_allocate_reg(var, forbidden_vars, selected_reg,
- need_lower_byte)
-
- def allocate_scratch_reg(self, type=INT, forbidden_vars=[], selected_reg=None):
- assert type == INT # XXX extend this once floats are supported
- return self.rm.allocate_scratch_reg(type=type,
- forbidden_vars=forbidden_vars,
- selected_reg=selected_reg)
-
- def _check_invariants(self):
- self.rm._check_invariants()
-
- def loc(self, var):
- if var.type == FLOAT:
- assert 0, "not implemented yet"
- return self.rm.loc(var)
-
- def position(self):
- return self.rm.position
-
- def next_instruction(self):
- self.rm.next_instruction()
-
- def force_spill_var(self, var):
- if var.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- self.rm.force_spill_var(var)
-
- def before_call(self, force_store=[], save_all_regs=False):
- self.rm.before_call(force_store, save_all_regs)
-
- def after_call(self, v):
- if v.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- return self.rm.after_call(v)
-
- def call_result_location(self, v):
- if v.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- return self.rm.call_result_location(v)
-
- def _ensure_value_is_boxed(self, thing, forbidden_vars=[]):
- if thing.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- return self.rm.ensure_value_is_boxed(thing, forbidden_vars)
-
- def get_scratch_reg(self, type, forbidden_vars=[], selected_reg=None):
- if type == FLOAT:
- assert 0, "not implemented yet"
- else:
- return self.rm.get_scratch_reg(type, forbidden_vars, selected_reg)
-
- def free_temp_vars(self):
- self.rm.free_temp_vars()
-
- def make_sure_var_in_reg(self, var, forbidden_vars=[],
- selected_reg=None, need_lower_byte=False):
- if var.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- return self.rm.make_sure_var_in_reg(var, forbidden_vars,
- selected_reg, need_lower_byte)
-
- def convert_to_imm(self, value):
- if isinstance(value, ConstInt):
- return self.rm.convert_to_imm(value)
- else:
- assert 0, "not implemented yet"
-
- def _sync_var(self, v):
- if v.type == FLOAT:
- assert 0, "not implemented yet"
- else:
- self.rm._sync_var(v)
-
- # ******************************************************
- # * P R E P A R E O P E R A T I O N S *
- # ******************************************************
-
-
- def void(self, op):
- return []
-
- prepare_int_add = prepare_binary_int_op_with_imm()
- prepare_int_sub = prepare_binary_int_op_with_imm()
- prepare_int_floordiv = prepare_binary_int_op_with_imm()
-
- prepare_int_mul = prepare_binary_int_op()
- prepare_int_mod = prepare_binary_int_op()
- prepare_int_and = prepare_binary_int_op()
- prepare_int_or = prepare_binary_int_op()
- prepare_int_xor = prepare_binary_int_op()
- prepare_int_lshift = prepare_binary_int_op()
- prepare_int_rshift = prepare_binary_int_op()
- prepare_uint_rshift = prepare_binary_int_op()
- prepare_uint_floordiv = prepare_binary_int_op()
-
- prepare_int_add_ovf = prepare_binary_int_op()
- prepare_int_sub_ovf = prepare_binary_int_op()
- prepare_int_mul_ovf = prepare_binary_int_op()
-
- prepare_int_neg = prepare_unary_int_op()
- prepare_int_invert = prepare_unary_int_op()
-
- prepare_int_le = prepare_cmp_op()
- prepare_int_lt = prepare_cmp_op()
- prepare_int_ge = prepare_cmp_op()
- prepare_int_gt = prepare_cmp_op()
- prepare_int_eq = prepare_cmp_op()
- prepare_int_ne = prepare_cmp_op()
-
- prepare_ptr_eq = prepare_int_eq
- prepare_ptr_ne = prepare_int_ne
-
- prepare_instance_ptr_eq = prepare_ptr_eq
- prepare_instance_ptr_ne = prepare_ptr_ne
-
- prepare_uint_lt = prepare_cmp_op()
- prepare_uint_le = prepare_cmp_op()
- prepare_uint_gt = prepare_cmp_op()
- prepare_uint_ge = prepare_cmp_op()
-
- prepare_int_is_true = prepare_unary_cmp()
- prepare_int_is_zero = prepare_unary_cmp()
-
- def prepare_finish(self, op):
- args = [None] * (op.numargs() + 1)
- for i in range(op.numargs()):
- arg = op.getarg(i)
- if arg:
- args[i] = self.loc(arg)
- self.possibly_free_var(arg)
- n = self.cpu.get_fail_descr_number(op.getdescr())
- args[-1] = imm(n)
- return args
-
- def prepare_call_malloc_gc(self, op):
- args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
- return args
-
- def _prepare_guard(self, op, args=None):
- if args is None:
- args = []
- args.append(imm(len(self.frame_manager.used)))
- for arg in op.getfailargs():
- if arg:
- args.append(self.loc(arg))
- else:
- args.append(None)
- return args
-
- def prepare_guard_true(self, op):
- l0 = self._ensure_value_is_boxed(op.getarg(0))
- args = self._prepare_guard(op, [l0])
- return args
-
- prepare_guard_false = prepare_guard_true
- prepare_guard_nonnull = prepare_guard_true
- prepare_guard_isnull = prepare_guard_true
-
- def prepare_guard_no_overflow(self, op):
- locs = self._prepare_guard(op)
- self.possibly_free_vars(op.getfailargs())
- return locs
-
- prepare_guard_overflow = prepare_guard_no_overflow
- prepare_guard_not_invalidated = prepare_guard_no_overflow
-
- def prepare_guard_exception(self, op):
- boxes = list(op.getarglist())
- arg0 = ConstInt(rffi.cast(lltype.Signed, op.getarg(0).getint()))
- loc = self._ensure_value_is_boxed(arg0)
- loc1 = self.get_scratch_reg(INT, boxes)
- if op.result in self.longevity:
- resloc = self.force_allocate_reg(op.result, boxes)
- self.possibly_free_var(op.result)
- else:
- resloc = None
- pos_exc_value = imm(self.cpu.pos_exc_value())
- pos_exception = imm(self.cpu.pos_exception())
- arglocs = self._prepare_guard(op,
- [loc, loc1, resloc, pos_exc_value, pos_exception])
- return arglocs
-
- def prepare_guard_no_exception(self, op):
- loc = self._ensure_value_is_boxed(
- ConstInt(self.cpu.pos_exception()))
- arglocs = self._prepare_guard(op, [loc])
- return arglocs
-
- def prepare_guard_value(self, op):
- boxes = list(op.getarglist())
- a0, a1 = boxes
- imm_a1 = check_imm_box(a1)
- l0 = self._ensure_value_is_boxed(a0, boxes)
- if not imm_a1:
- l1 = self._ensure_value_is_boxed(a1, boxes)
- else:
- l1 = self.make_sure_var_in_reg(a1, boxes)
- assert op.result is None
- arglocs = self._prepare_guard(op, [l0, l1])
- self.possibly_free_vars(op.getarglist())
- self.possibly_free_vars(op.getfailargs())
- return arglocs
-
- def prepare_guard_class(self, op):
- assert isinstance(op.getarg(0), Box)
- boxes = list(op.getarglist())
- x = self._ensure_value_is_boxed(boxes[0], boxes)
- y = self.get_scratch_reg(REF, forbidden_vars=boxes)
- y_val = rffi.cast(lltype.Signed, op.getarg(1).getint())
- self.assembler.load(y, imm(y_val))
- offset = self.cpu.vtable_offset
- assert offset is not None
- offset_loc = self._ensure_value_is_boxed(ConstInt(offset), boxes)
- arglocs = self._prepare_guard(op, [x, y, offset_loc])
- return arglocs
-
- prepare_guard_nonnull_class = prepare_guard_class
-
- def compute_hint_frame_locations(self, operations):
- # optimization only: fill in the 'hint_frame_locations' dictionary
- # of rm and xrm based on the JUMP at the end of the loop, by looking
- # at where we would like the boxes to be after the jump.
- op = operations[-1]
- if op.getopnum() != rop.JUMP:
- return
- self.final_jump_op = op
- descr = op.getdescr()
- assert isinstance(descr, TargetToken)
- if descr._ppc_loop_code != 0:
- # if the target LABEL was already compiled, i.e. if it belongs
- # to some already-compiled piece of code
- self._compute_hint_frame_locations_from_descr(descr)
- #else:
- # The loop ends in a JUMP going back to a LABEL in the same loop.
- # We cannot fill 'hint_frame_locations' immediately, but we can
- # wait until the corresponding prepare_op_label() to know where the
- # we would like the boxes to be after the jump.
-
- def _compute_hint_frame_locations_from_descr(self, descr):
- arglocs = self.assembler.target_arglocs(descr)
- jump_op = self.final_jump_op
- assert len(arglocs) == jump_op.numargs()
- for i in range(jump_op.numargs()):
- box = jump_op.getarg(i)
- if isinstance(box, Box):
- loc = arglocs[i]
- if loc is not None and loc.is_stack():
- self.frame_manager.hint_frame_locations[box] = loc
-
- def prepare_guard_call_release_gil(self, op, guard_op):
- # first, close the stack in the sense of the asmgcc GC root tracker
- gcrootmap = self.cpu.gc_ll_descr.gcrootmap
- if gcrootmap:
- arglocs = []
- argboxes = []
- for i in range(op.numargs()):
- loc, box = self._ensure_value_is_boxed(op.getarg(i), argboxes)
- arglocs.append(loc)
- argboxes.append(box)
- self.assembler.call_release_gil(gcrootmap, arglocs, fcond)
- self.possibly_free_vars(argboxes)
- # do the call
- faildescr = guard_op.getdescr()
- fail_index = self.cpu.get_fail_descr_number(faildescr)
- self.assembler._write_fail_index(fail_index)
- args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
- self.assembler.emit_call(op, args, self, fail_index)
- # then reopen the stack
- if gcrootmap:
- self.assembler.call_reacquire_gil(gcrootmap, r.r0, fcond)
- locs = self._prepare_guard(guard_op)
- self.possibly_free_vars(guard_op.getfailargs())
- return locs
-
- def prepare_jump(self, op):
- descr = op.getdescr()
- assert isinstance(descr, TargetToken)
- self.jump_target_descr = descr
- arglocs = self.assembler.target_arglocs(descr)
-
- # get temporary locs
- tmploc = r.SCRATCH
-
- # Part about non-floats
- src_locations1 = []
- dst_locations1 = []
-
- # Build the four lists
- for i in range(op.numargs()):
- box = op.getarg(i)
- src_loc = self.loc(box)
- dst_loc = arglocs[i]
- if box.type != FLOAT:
- src_locations1.append(src_loc)
- dst_locations1.append(dst_loc)
- else:
- assert 0, "not implemented yet"
-
- remap_frame_layout(self.assembler, src_locations1,
- dst_locations1, tmploc)
- return []
-
- def prepare_setfield_gc(self, op):
- boxes = list(op.getarglist())
- a0, a1 = boxes
- ofs, size, sign = unpack_fielddescr(op.getdescr())
- base_loc = self._ensure_value_is_boxed(a0, boxes)
- value_loc = self._ensure_value_is_boxed(a1, boxes)
- if _check_imm_arg(ofs):
- ofs_loc = imm(ofs)
- else:
- ofs_loc = self.get_scratch_reg(INT, boxes)
- self.assembler.load(ofs_loc, imm(ofs))
- return [value_loc, base_loc, ofs_loc, imm(size)]
-
- prepare_setfield_raw = prepare_setfield_gc
-
- def prepare_getfield_gc(self, op):
- a0 = op.getarg(0)
- ofs, size, sign = unpack_fielddescr(op.getdescr())
- base_loc = self._ensure_value_is_boxed(a0)
- immofs = imm(ofs)
- if _check_imm_arg(ofs):
- ofs_loc = immofs
- else:
- ofs_loc = self.get_scratch_reg(INT, [a0])
- self.assembler.load(ofs_loc, immofs)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
- return [base_loc, ofs_loc, res, imm(size)]
-
- prepare_getfield_raw = prepare_getfield_gc
- prepare_getfield_raw_pure = prepare_getfield_gc
- prepare_getfield_gc_pure = prepare_getfield_gc
-
- def prepare_getinteriorfield_gc(self, op):
- t = unpack_interiorfielddescr(op.getdescr())
- ofs, itemsize, fieldsize, sign = t
- args = op.getarglist()
- base_loc = self._ensure_value_is_boxed(op.getarg(0), args)
- index_loc = self._ensure_value_is_boxed(op.getarg(1), args)
- c_ofs = ConstInt(ofs)
- if _check_imm_arg(c_ofs):
- ofs_loc = imm(ofs)
- else:
- ofs_loc = self._ensure_value_is_boxed(c_ofs, args)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- result_loc = self.force_allocate_reg(op.result)
- self.possibly_free_var(op.result)
- return [base_loc, index_loc, result_loc, ofs_loc, imm(ofs),
- imm(itemsize), imm(fieldsize)]
-
- def prepare_setinteriorfield_gc(self, op):
- t = unpack_interiorfielddescr(op.getdescr())
- ofs, itemsize, fieldsize, sign = t
- args = op.getarglist()
- base_loc = self._ensure_value_is_boxed(op.getarg(0), args)
- index_loc = self._ensure_value_is_boxed(op.getarg(1), args)
- value_loc = self._ensure_value_is_boxed(op.getarg(2), args)
- c_ofs = ConstInt(ofs)
- if _check_imm_arg(c_ofs):
- ofs_loc = imm(ofs)
- else:
- ofs_loc = self._ensure_value_is_boxed(c_ofs, args)
- return [base_loc, index_loc, value_loc, ofs_loc, imm(ofs),
- imm(itemsize), imm(fieldsize)]
-
- def prepare_arraylen_gc(self, op):
- arraydescr = op.getdescr()
- assert isinstance(arraydescr, ArrayDescr)
- ofs = arraydescr.lendescr.offset
- arg = op.getarg(0)
- base_loc = self._ensure_value_is_boxed(arg)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
- return [res, base_loc, imm(ofs)]
-
- def prepare_setarrayitem_gc(self, op):
- a0, a1, a2 = list(op.getarglist())
- size, ofs, _ = unpack_arraydescr(op.getdescr())
- scale = get_scale(size)
- args = op.getarglist()
- base_loc = self._ensure_value_is_boxed(a0, args)
- ofs_loc = self._ensure_value_is_boxed(a1, args)
- scratch_loc = self.rm.get_scratch_reg(INT, [base_loc, ofs_loc])
- value_loc = self._ensure_value_is_boxed(a2, args)
- assert _check_imm_arg(ofs)
- return [value_loc, base_loc, ofs_loc, scratch_loc,
- imm(scale), imm(ofs)]
-
- prepare_setarrayitem_raw = prepare_setarrayitem_gc
-
- def prepare_getarrayitem_gc(self, op):
- a0, a1 = boxes = list(op.getarglist())
- size, ofs, _ = unpack_arraydescr(op.getdescr())
- scale = get_scale(size)
- base_loc = self._ensure_value_is_boxed(a0, boxes)
- ofs_loc = self._ensure_value_is_boxed(a1, boxes)
- scratch_loc = self.rm.get_scratch_reg(INT, [base_loc, ofs_loc])
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
- assert _check_imm_arg(ofs)
- return [res, base_loc, ofs_loc, scratch_loc,
- imm(scale), imm(ofs)]
-
- prepare_getarrayitem_raw = prepare_getarrayitem_gc
- prepare_getarrayitem_gc_pure = prepare_getarrayitem_gc
-
- def prepare_strlen(self, op):
- args = op.getarglist()
- l0 = self._ensure_value_is_boxed(op.getarg(0))
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
- self.cpu.translate_support_code)
- immofs = imm(ofs_length)
- if _check_imm_arg(ofs_length):
- l1 = immofs
- else:
- l1 = self.get_scratch_reg(INT, args)
- self.assembler.load(l1, immofs)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
-
- res = self.force_allocate_reg(op.result)
- self.possibly_free_var(op.result)
- return [l0, l1, res]
-
- def prepare_strgetitem(self, op):
- boxes = list(op.getarglist())
- base_loc = self._ensure_value_is_boxed(boxes[0])
-
- a1 = boxes[1]
- imm_a1 = check_imm_box(a1)
- if imm_a1:
- ofs_loc = self.make_sure_var_in_reg(a1, boxes)
- else:
- ofs_loc = self._ensure_value_is_boxed(a1, boxes)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
-
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
- self.cpu.translate_support_code)
- assert itemsize == 1
- return [res, base_loc, ofs_loc, imm(basesize)]
-
- def prepare_strsetitem(self, op):
- boxes = list(op.getarglist())
- base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
- ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
- value_loc = self._ensure_value_is_boxed(boxes[2], boxes)
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
- self.cpu.translate_support_code)
- assert itemsize == 1
- return [value_loc, base_loc, ofs_loc, imm(basesize)]
-
- prepare_copystrcontent = void
- prepare_copyunicodecontent = void
-
- def prepare_unicodelen(self, op):
- l0 = self._ensure_value_is_boxed(op.getarg(0))
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
- self.cpu.translate_support_code)
- immofs = imm(ofs_length)
- if _check_imm_arg(ofs_length):
- l1 = immofs
- else:
- l1 = self.get_scratch_reg(INT, [op.getarg(0)])
- self.assembler.load(l1, immofs)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
- return [l0, l1, res]
-
- def prepare_unicodegetitem(self, op):
- boxes = list(op.getarglist())
- base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
- ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op.result)
-
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
- self.cpu.translate_support_code)
- scale = itemsize / 2
- return [res, base_loc, ofs_loc,
- imm(scale), imm(basesize), imm(itemsize)]
-
- def prepare_unicodesetitem(self, op):
- boxes = list(op.getarglist())
- base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
- ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
- value_loc = self._ensure_value_is_boxed(boxes[2], boxes)
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
- self.cpu.translate_support_code)
- scale = itemsize / 2
- return [value_loc, base_loc, ofs_loc,
- imm(scale), imm(basesize), imm(itemsize)]
-
- def prepare_same_as(self, op):
- arg = op.getarg(0)
- imm_arg = _check_imm_arg(arg)
- if imm_arg:
- argloc = self.make_sure_var_in_reg(arg)
- else:
- argloc = self._ensure_value_is_boxed(arg)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- resloc = self.force_allocate_reg(op.result)
- return [argloc, resloc]
-
- prepare_cast_ptr_to_int = prepare_same_as
- prepare_cast_int_to_ptr = prepare_same_as
-
- def prepare_call(self, op):
- effectinfo = op.getdescr().get_extra_info()
- if effectinfo is not None:
- oopspecindex = effectinfo.oopspecindex
- if oopspecindex == EffectInfo.OS_MATH_SQRT:
- args = self.prepare_op_math_sqrt(op, fcond)
- self.assembler.emit_op_math_sqrt(op, args, self, fcond)
- return
- args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
- return args
-
- prepare_debug_merge_point = void
- prepare_jit_debug = void
-
- def prepare_cond_call_gc_wb(self, op):
- assert op.result is None
- N = op.numargs()
- # we force all arguments in a reg (unless they are Consts),
- # because it will be needed anyway by the following setfield_gc
- # or setarrayitem_gc. It avoids loading it twice from the memory.
- arglocs = []
- argboxes = []
- for i in range(N):
- loc = self._ensure_value_is_boxed(op.getarg(i), argboxes)
- arglocs.append(loc)
- self.rm.possibly_free_vars(argboxes)
- return arglocs
-
- prepare_cond_call_gc_wb_array = prepare_cond_call_gc_wb
-
- def prepare_force_token(self, op):
- res_loc = self.force_allocate_reg(op.result)
- self.possibly_free_var(op.result)
- return [res_loc]
-
- def prepare_label(self, op):
- # XXX big refactoring needed?
- descr = op.getdescr()
- assert isinstance(descr, TargetToken)
- inputargs = op.getarglist()
- arglocs = [None] * len(inputargs)
- #
- # we use force_spill() on the boxes that are not going to be really
- # used any more in the loop, but that are kept alive anyway
- # by being in a next LABEL's or a JUMP's argument or fail_args
- # of some guard
- position = self.rm.position
- for arg in inputargs:
- assert isinstance(arg, Box)
- if self.last_real_usage.get(arg, -1) <= position:
- self.force_spill_var(arg)
-
- #
- for i in range(len(inputargs)):
- arg = inputargs[i]
- assert isinstance(arg, Box)
- loc = self.loc(arg)
- arglocs[i] = loc
- if loc.is_reg():
- self.frame_manager.mark_as_free(arg)
- #
- descr._ppc_arglocs = arglocs
- descr._ppc_loop_code = self.assembler.mc.currpos()
- descr._ppc_clt = self.assembler.current_clt
- self.assembler.target_tokens_currently_compiling[descr] = None
- self.possibly_free_vars_for_op(op)
- #
- # if the LABEL's descr is precisely the target of the JUMP at the
- # end of the same loop, i.e. if what we are compiling is a single
- # loop that ends up jumping to this LABEL, then we can now provide
- # the hints about the expected position of the spilled variables.
- jump_op = self.final_jump_op
- if jump_op is not None and jump_op.getdescr() is descr:
- self._compute_hint_frame_locations_from_descr(descr)
-
- def prepare_guard_call_may_force(self, op, guard_op):
- faildescr = guard_op.getdescr()
- fail_index = self.cpu.get_fail_descr_number(faildescr)
- self.assembler._write_fail_index(fail_index)
- args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
- for v in guard_op.getfailargs():
- if v in self.rm.reg_bindings:
- self.force_spill_var(v)
- self.assembler.emit_call(op, args, self, fail_index)
- locs = self._prepare_guard(guard_op)
- self.possibly_free_vars(guard_op.getfailargs())
- return locs
-
- def prepare_guard_call_assembler(self, op, guard_op):
- descr = op.getdescr()
- assert isinstance(descr, JitCellToken)
- jd = descr.outermost_jitdriver_sd
- assert jd is not None
- #size = jd.portal_calldescr.get_result_size(self.cpu.translate_support_code)
- size = jd.portal_calldescr.get_result_size()
- vable_index = jd.index_of_virtualizable
- if vable_index >= 0:
- self._sync_var(op.getarg(vable_index))
- vable = self.frame_manager.loc(op.getarg(vable_index))
- else:
- vable = imm(0)
- self.possibly_free_vars(guard_op.getfailargs())
- return [imm(size), vable]
-
- def _prepare_args_for_new_op(self, new_args):
- gc_ll_descr = self.cpu.gc_ll_descr
- args = gc_ll_descr.args_for_new(new_args)
- arglocs = []
- for i in range(len(args)):
- arg = args[i]
- t = TempInt()
- l = self.force_allocate_reg(t, selected_reg=r.MANAGED_REGS[i])
- self.assembler.load(l, imm(arg))
- arglocs.append(t)
- return arglocs
-
- def _malloc_varsize(self, ofs_items, ofs_length, itemsize, op):
- v = op.getarg(0)
- res_v = op.result
- boxes = [v, res_v]
- itemsize_box = ConstInt(itemsize)
- ofs_items_box = ConstInt(ofs_items)
- if _check_imm_arg(ofs_items_box):
- ofs_items_loc = self.convert_to_imm(ofs_items_box)
- else:
- ofs_items_loc, ofs_items_box = self._ensure_value_is_boxed(ofs_items_box, boxes)
- boxes.append(ofs_items_box)
- vloc, vbox = self._ensure_value_is_boxed(v, [res_v])
- boxes.append(vbox)
- size, size_box = self._ensure_value_is_boxed(itemsize_box, boxes)
- boxes.append(size_box)
- self.assembler._regalloc_malloc_varsize(size, size_box,
- vloc, vbox, ofs_items_loc, self, res_v)
- base_loc = self.make_sure_var_in_reg(res_v)
-
- value_loc, vbox = self._ensure_value_is_boxed(v, [res_v])
- boxes.append(vbox)
- self.possibly_free_vars(boxes)
- assert value_loc.is_reg()
- assert base_loc.is_reg()
- return [value_loc, base_loc, imm(ofs_length)]
-
- # from ../x86/regalloc.py:791
- def _unpack_fielddescr(self, fielddescr):
- assert isinstance(fielddescr, BaseFieldDescr)
- ofs = fielddescr.offset
- size = fielddescr.get_field_size(self.cpu.translate_support_code)
- ptr = fielddescr.is_pointer_field()
- return ofs, size, ptr
-
- # from ../x86/regalloc.py:779
- def _unpack_arraydescr(self, arraydescr):
- assert isinstance(arraydescr, BaseArrayDescr)
- cpu = self.cpu
- ofs_length = arraydescr.get_ofs_length(cpu.translate_support_code)
- ofs = arraydescr.get_base_size(cpu.translate_support_code)
- size = arraydescr.get_item_size(cpu.translate_support_code)
- ptr = arraydescr.is_array_of_pointers()
- scale = 0
- while (1 << scale) < size:
- scale += 1
- assert (1 << scale) == size
- return size, scale, ofs, ofs_length, ptr
-
- def prepare_force_spill(self, op):
- self.force_spill_var(op.getarg(0))
- return []
-
-def add_none_argument(fn):
- return lambda self, op: fn(self, op, None)
-
-def notimplemented(self, op):
- raise NotImplementedError, op
-
-def notimplemented_with_guard(self, op, guard_op):
-
- raise NotImplementedError, op
-
-operations = [notimplemented] * (rop._LAST + 1)
-operations_with_guard = [notimplemented_with_guard] * (rop._LAST + 1)
-
-def get_scale(size):
- scale = 0
- while (1 << scale) < size:
- scale += 1
- assert (1 << scale) == size
- return scale
-
-for key, value in rop.__dict__.items():
- key = key.lower()
- if key.startswith('_'):
- continue
- methname = 'prepare_%s' % key
- if hasattr(Regalloc, methname):
- func = getattr(Regalloc, methname).im_func
- operations[value] = func
-
-for key, value in rop.__dict__.items():
- key = key.lower()
- if key.startswith('_'):
- continue
- methname = 'prepare_guard_%s' % key
- if hasattr(Regalloc, methname):
- func = getattr(Regalloc, methname).im_func
- operations_with_guard[value] = func
- operations[value] = add_none_argument(func)
-
-Regalloc.operations = operations
-Regalloc.operations_with_guard = operations_with_guard
diff --git a/pypy/jit/backend/ppc/ppcgen/test/__init__.py b/pypy/jit/backend/ppc/ppcgen/test/__init__.py
deleted file mode 100644
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_rassemblermaker.py b/pypy/jit/backend/ppc/ppcgen/test/test_rassemblermaker.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/ppcgen/test/test_rassemblermaker.py
+++ /dev/null
@@ -1,39 +0,0 @@
-from pypy.jit.backend.ppc.ppcgen.rassemblermaker import make_rassembler
-from pypy.jit.backend.ppc.ppcgen.ppc_assembler import PPCAssembler
-
-RPPCAssembler = make_rassembler(PPCAssembler)
-
-_a = PPCAssembler()
-_a.add(3, 3, 4)
-add_r3_r3_r4 = _a.insts[0].assemble()
-
-def test_simple():
- ra = RPPCAssembler()
- ra.add(3, 3, 4)
- assert ra.insts == [add_r3_r3_r4]
-
-def test_rtyped():
- from pypy.rpython.test.test_llinterp import interpret
- def f():
- ra = RPPCAssembler()
- ra.add(3, 3, 4)
- ra.lwz(1, 1, 1) # ensure that high bit doesn't produce long but r_uint
- return ra.insts[0]
- res = interpret(f, [])
- assert res == add_r3_r3_r4
-
-def test_mnemonic():
- mrs = []
- for A in PPCAssembler, RPPCAssembler:
- a = A()
- a.mr(3, 4)
- mrs.append(a.insts[0])
- assert mrs[0].assemble() == mrs[1]
-
-def test_spr_coding():
- mrs = []
- for A in PPCAssembler, RPPCAssembler:
- a = A()
- a.mtctr(3)
- mrs.append(a.insts[0])
- assert mrs[0].assemble() == mrs[1]
diff --git a/pypy/jit/backend/ppc/regalloc.py b/pypy/jit/backend/ppc/regalloc.py
--- a/pypy/jit/backend/ppc/regalloc.py
+++ b/pypy/jit/backend/ppc/regalloc.py
@@ -1,213 +1,948 @@
-from pypy.jit.codegen.ppc.instruction import \
- gprs, fprs, crfs, ctr, \
- NO_REGISTER, GP_REGISTER, FP_REGISTER, CR_FIELD, CT_REGISTER, \
- CMPInsn, Spill, Unspill, stack_slot, \
- rSCRATCH
+from pypy.jit.backend.llsupport.regalloc import (RegisterManager, FrameManager,
+ TempBox, compute_vars_longevity)
+from pypy.jit.backend.ppc.arch import (WORD, MY_COPY_OF_REGS)
+from pypy.jit.backend.ppc.jump import (remap_frame_layout_mixed,
+ remap_frame_layout)
+from pypy.jit.backend.ppc.locations import imm
+from pypy.jit.backend.ppc.helper.regalloc import (_check_imm_arg,
+ check_imm_box,
+ prepare_cmp_op,
+ prepare_unary_int_op,
+ prepare_binary_int_op,
+ prepare_binary_int_op_with_imm,
+ prepare_unary_cmp)
+from pypy.jit.metainterp.history import (INT, REF, FLOAT, Const, ConstInt,
+ ConstPtr, Box)
+from pypy.jit.metainterp.history import JitCellToken, TargetToken
+from pypy.jit.metainterp.resoperation import rop
+from pypy.jit.backend.ppc import locations
+from pypy.rpython.lltypesystem import rffi, lltype, rstr
+from pypy.jit.backend.llsupport import symbolic
+from pypy.jit.backend.llsupport.descr import ArrayDescr
+from pypy.jit.codewriter.effectinfo import EffectInfo
+import pypy.jit.backend.ppc.register as r
+from pypy.jit.codewriter import heaptracker
+from pypy.jit.backend.llsupport.descr import unpack_arraydescr
+from pypy.jit.backend.llsupport.descr import unpack_fielddescr
+from pypy.jit.backend.llsupport.descr import unpack_interiorfielddescr
-from pypy.jit.codegen.ppc.conftest import option
+# xxx hack: set a default value for TargetToken._arm_loop_code. If 0, we know
+# that it is a LABEL that was not compiled yet.
+TargetToken._ppc_loop_code = 0
-DEBUG_PRINT = option.debug_print
+class TempInt(TempBox):
+ type = INT
-class RegisterAllocation:
- def __init__(self, freeregs, initial_mapping, initial_spill_offset):
- if DEBUG_PRINT:
- print
- print "RegisterAllocation __init__", initial_mapping.items()
+ def __repr__(self):
+ return "<TempInt at %s>" % (id(self),)
- self.insns = [] # output list of instructions
+class TempPtr(TempBox):
+ type = REF
- # registers with dead values
- self.freeregs = {}
- for regcls in freeregs:
- self.freeregs[regcls] = freeregs[regcls][:]
+ def __repr__(self):
+ return "<TempPtr at %s>" % (id(self),)
- self.var2loc = {} # maps Vars to AllocationSlots
- self.lru = [] # least-recently-used list of vars; first is oldest.
- # contains all vars in registers, and no vars on stack
+class PPCRegisterManager(RegisterManager):
+ all_regs = r.MANAGED_REGS
+ box_types = None # or a list of acceptable types
+ no_lower_byte_regs = all_regs
+ save_around_call_regs = r.VOLATILES
- self.spill_offset = initial_spill_offset # where to put next spilled
- # value, relative to rFP,
- # measured in bytes
- self.free_stack_slots = [] # a free list for stack slots
+ REGLOC_TO_COPY_AREA_OFS = {
+ r.r0: MY_COPY_OF_REGS + 0 * WORD,
+ r.r2: MY_COPY_OF_REGS + 1 * WORD,
+ r.r3: MY_COPY_OF_REGS + 2 * WORD,
+ r.r4: MY_COPY_OF_REGS + 3 * WORD,
+ r.r5: MY_COPY_OF_REGS + 4 * WORD,
+ r.r6: MY_COPY_OF_REGS + 5 * WORD,
+ r.r7: MY_COPY_OF_REGS + 6 * WORD,
+ r.r8: MY_COPY_OF_REGS + 7 * WORD,
+ r.r9: MY_COPY_OF_REGS + 8 * WORD,
+ r.r10: MY_COPY_OF_REGS + 9 * WORD,
+ r.r11: MY_COPY_OF_REGS + 10 * WORD,
+ r.r12: MY_COPY_OF_REGS + 11 * WORD,
+ r.r13: MY_COPY_OF_REGS + 12 * WORD,
+ r.r14: MY_COPY_OF_REGS + 13 * WORD,
+ r.r15: MY_COPY_OF_REGS + 14 * WORD,
+ r.r16: MY_COPY_OF_REGS + 15 * WORD,
+ r.r17: MY_COPY_OF_REGS + 16 * WORD,
+ r.r18: MY_COPY_OF_REGS + 17 * WORD,
+ r.r19: MY_COPY_OF_REGS + 18 * WORD,
+ r.r20: MY_COPY_OF_REGS + 19 * WORD,
+ r.r21: MY_COPY_OF_REGS + 20 * WORD,
+ r.r22: MY_COPY_OF_REGS + 21 * WORD,
+ r.r23: MY_COPY_OF_REGS + 22 * WORD,
+ r.r24: MY_COPY_OF_REGS + 23 * WORD,
+ r.r25: MY_COPY_OF_REGS + 24 * WORD,
+ r.r26: MY_COPY_OF_REGS + 25 * WORD,
+ r.r27: MY_COPY_OF_REGS + 26 * WORD,
+ r.r28: MY_COPY_OF_REGS + 27 * WORD,
+ r.r29: MY_COPY_OF_REGS + 28 * WORD,
+ r.r30: MY_COPY_OF_REGS + 29 * WORD,
+ r.r31: MY_COPY_OF_REGS + 30 * WORD,
+ }
- # go through the initial mapping and initialize the data structures
- for var, loc in initial_mapping.iteritems():
- self.set(var, loc)
- if loc.is_register:
- if loc.alloc in self.freeregs[loc.regclass]:
- self.freeregs[loc.regclass].remove(loc.alloc)
- self.lru.append(var)
+ def __init__(self, longevity, frame_manager=None, assembler=None):
+ RegisterManager.__init__(self, longevity, frame_manager, assembler)
+
+ def call_result_location(self, v):
+ return r.r3
+
+ def convert_to_imm(self, c):
+ if isinstance(c, ConstInt):
+ val = rffi.cast(lltype.Signed, c.value)
+ return locations.ImmLocation(val)
+ else:
+ assert isinstance(c, ConstPtr)
+ return locations.ImmLocation(rffi.cast(lltype.Signed, c.value))
+
+ def ensure_value_is_boxed(self, thing, forbidden_vars=None):
+ loc = None
+ if isinstance(thing, Const):
+ if isinstance(thing, ConstPtr):
+ tp = REF
else:
- assert loc.offset >= self.spill_offset
+ tp = INT
+ loc = self.get_scratch_reg(tp, forbidden_vars=self.temp_boxes
+ + forbidden_vars)
+ immvalue = self.convert_to_imm(thing)
+ self.assembler.load(loc, immvalue)
+ else:
+ loc = self.make_sure_var_in_reg(thing,
+ forbidden_vars=self.temp_boxes + forbidden_vars)
+ return loc
- self.labels_to_tell_spill_offset_to = []
- self.builders_to_tell_spill_offset_to = []
+ def allocate_scratch_reg(self, type=INT, selected_reg=None, forbidden_vars=None):
+ """Allocate a scratch register, possibly spilling a managed register.
+ This register is freed after emitting the current operation and can not
+ be spilled"""
+ box = TempBox()
+ reg = self.force_allocate_reg(box,
+ selected_reg=selected_reg,
+ forbidden_vars=forbidden_vars)
+ return reg, box
- def set(self, var, loc):
- assert var not in self.var2loc
- self.var2loc[var] = loc
-
- def forget(self, var, loc):
- assert self.var2loc[var] is loc
- del self.var2loc[var]
-
- def loc_of(self, var):
- return self.var2loc[var]
-
- def spill_slot(self):
- """ Returns an unused stack location. """
- if self.free_stack_slots:
- return self.free_stack_slots.pop()
- else:
- self.spill_offset -= 4
- return stack_slot(self.spill_offset)
-
- def spill(self, reg, argtospill):
- if argtospill in self.lru:
- self.lru.remove(argtospill)
- self.forget(argtospill, reg)
- spillslot = self.spill_slot()
- if reg.regclass != GP_REGISTER:
- self.insns.append(reg.move_to_gpr(0))
- reg = gprs[0]
- self.insns.append(Spill(argtospill, reg, spillslot))
- self.set(argtospill, spillslot)
-
- def _allocate_reg(self, regclass, newarg):
-
- # check if there is a register available
- freeregs = self.freeregs[regclass]
-
- if freeregs:
- reg = freeregs.pop().make_loc()
- self.set(newarg, reg)
- if DEBUG_PRINT:
- print "allocate_reg: Putting %r into fresh register %r" % (newarg, reg)
- return reg
-
- # if not, find something to spill
- for i in range(len(self.lru)):
- argtospill = self.lru[i]
- reg = self.loc_of(argtospill)
- assert reg.is_register
- if reg.regclass == regclass:
- del self.lru[i]
- break
- else:
- assert 0
-
- # Move the value we are spilling onto the stack, both in the
- # data structures and in the instructions:
-
- self.spill(reg, argtospill)
-
- if DEBUG_PRINT:
- print "allocate_reg: Spilled %r from %r to %r." % (argtospill, reg, self.loc_of(argtospill))
-
- # update data structures to put newarg into the register
- reg = reg.alloc.make_loc()
- self.set(newarg, reg)
- if DEBUG_PRINT:
- print "allocate_reg: Put %r in stolen reg %r." % (newarg, reg)
+ def get_scratch_reg(self, type=INT, forbidden_vars=[], selected_reg=None):
+ assert type == INT or type == REF
+ box = TempBox()
+ self.temp_boxes.append(box)
+ reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
+ selected_reg=selected_reg)
return reg
- def _promote(self, arg):
- if arg in self.lru:
- self.lru.remove(arg)
- self.lru.append(arg)
+class PPCFrameManager(FrameManager):
+ def __init__(self):
+ FrameManager.__init__(self)
+ self.used = []
- def allocate_for_insns(self, insns):
- from pypy.jit.codegen.ppc.rgenop import Var
+ @staticmethod
+ def frame_pos(loc, type):
+ num_words = PPCFrameManager.frame_size(type)
+ if type == FLOAT:
+ assert 0, "not implemented yet"
+ return locations.StackLocation(loc, num_words=num_words, type=type)
- insns2 = []
+ @staticmethod
+ def frame_size(type):
+ if type == FLOAT:
+ assert 0, "TODO"
+ return 1
- # make a pass through the instructions, loading constants into
- # Vars where needed.
- for insn in insns:
- newargs = []
- for arg in insn.reg_args:
- if not isinstance(arg, Var):
- newarg = Var()
- arg.load(insns2, newarg)
- newargs.append(newarg)
+ @staticmethod
+ def get_loc_index(loc):
+ assert loc.is_stack()
+ if loc.type == FLOAT:
+ assert 0, "not implemented yet"
+ return loc.position
+
+class Regalloc(object):
+
+ def __init__(self, frame_manager=None, assembler=None):
+ self.cpu = assembler.cpu
+ self.frame_manager = frame_manager
+ self.assembler = assembler
+ self.jump_target_descr = None
+ self.final_jump_op = None
+
+ def _prepare(self, inputargs, operations):
+ longevity, last_real_usage = compute_vars_longevity(
+ inputargs, operations)
+ self.longevity = longevity
+ self.last_real_usage = last_real_usage
+ fm = self.frame_manager
+ asm = self.assembler
+ self.rm = PPCRegisterManager(longevity, fm, asm)
+
+ def prepare_loop(self, inputargs, operations):
+ self._prepare(inputargs, operations)
+ self._set_initial_bindings(inputargs)
+ self.possibly_free_vars(list(inputargs))
+
+ def prepare_bridge(self, inputargs, arglocs, ops):
+ self._prepare(inputargs, ops)
+ self._update_bindings(arglocs, inputargs)
+
+ def _set_initial_bindings(self, inputargs):
+ arg_index = 0
+ count = 0
+ n_register_args = len(r.PARAM_REGS)
+ cur_frame_pos = -self.assembler.OFFSET_STACK_ARGS // WORD + 1
+ for box in inputargs:
+ assert isinstance(box, Box)
+ # handle inputargs in argument registers
+ if box.type == FLOAT and arg_index % 2 != 0:
+ assert 0, "not implemented yet"
+ if arg_index < n_register_args:
+ if box.type == FLOAT:
+ assert 0, "not implemented yet"
else:
- newargs.append(arg)
- insn.reg_args[0:len(newargs)] = newargs
- insns2.append(insn)
+ loc = r.PARAM_REGS[arg_index]
+ self.try_allocate_reg(box, selected_reg=loc)
+ arg_index += 1
+ else:
+ # treat stack args as stack locations with a negative offset
+ if box.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ cur_frame_pos -= 1
+ count += 1
+ loc = self.frame_manager.frame_pos(cur_frame_pos, box.type)
+ self.frame_manager.set_binding(box, loc)
- # Walk through instructions in forward order
- for insn in insns2:
+ def _update_bindings(self, locs, inputargs):
+ used = {}
+ i = 0
+ for loc in locs:
+ arg = inputargs[i]
+ i += 1
+ if loc.is_reg():
+ self.rm.reg_bindings[arg] = loc
+ elif loc.is_vfp_reg():
+ assert 0, "not supported"
+ else:
+ assert loc.is_stack()
+ self.frame_manager.set_binding(arg, loc)
+ used[loc] = None
- if DEBUG_PRINT:
- print "Processing instruction"
- print insn
- print "LRU list was:", self.lru
- print 'located at', [self.loc_of(a) for a in self.lru]
+ # XXX combine with x86 code and move to llsupport
+ self.rm.free_regs = []
+ for reg in self.rm.all_regs:
+ if reg not in used:
+ self.rm.free_regs.append(reg)
+ # note: we need to make a copy of inputargs because possibly_free_vars
+ # is also used on op args, which is a non-resizable list
+ self.possibly_free_vars(list(inputargs))
- # put things into the lru
- for arg in insn.reg_args:
- self._promote(arg)
- if insn.result:
- self._promote(insn.result)
- if DEBUG_PRINT:
- print "LRU list is now:", self.lru
- print 'located at', [self.loc_of(a) for a in self.lru if a is not insn.result]
+ def possibly_free_var(self, var):
+ self.rm.possibly_free_var(var)
- # We need to allocate a register for each used
- # argument that is not already in one
- for i in range(len(insn.reg_args)):
- arg = insn.reg_args[i]
- argcls = insn.reg_arg_regclasses[i]
- if DEBUG_PRINT:
- print "Allocating register for", arg, "..."
- argloc = self.loc_of(arg)
- if DEBUG_PRINT:
- print "currently in", argloc
+ def possibly_free_vars(self, vars):
+ for var in vars:
+ self.possibly_free_var(var)
- if not argloc.is_register:
- # It has no register now because it has been spilled
- self.forget(arg, argloc)
- newargloc = self._allocate_reg(argcls, arg)
- if DEBUG_PRINT:
- print "unspilling to", newargloc
- self.insns.append(Unspill(arg, newargloc, argloc))
- self.free_stack_slots.append(argloc)
- elif argloc.regclass != argcls:
- # it's in the wrong kind of register
- # (this code is excessively confusing)
- self.forget(arg, argloc)
- self.freeregs[argloc.regclass].append(argloc.alloc)
- if argloc.regclass != GP_REGISTER:
- if argcls == GP_REGISTER:
- gpr = self._allocate_reg(GP_REGISTER, arg).number
- else:
- gpr = rSCRATCH
- self.insns.append(
- argloc.move_to_gpr(gpr))
- else:
- gpr = argloc.number
- if argcls != GP_REGISTER:
- newargloc = self._allocate_reg(argcls, arg)
- self.insns.append(
- newargloc.move_from_gpr(gpr))
- else:
- if DEBUG_PRINT:
- print "it was in ", argloc
- pass
+ def possibly_free_vars_for_op(self, op):
+ for i in range(op.numargs()):
+ var = op.getarg(i)
+ if var is not None:
+ self.possibly_free_var(var)
- # Need to allocate a register for the destination
- assert not insn.result or insn.result not in self.var2loc
- if insn.result_regclass != NO_REGISTER:
- if DEBUG_PRINT:
- print "Allocating register for result %r..." % (insn.result,)
- resultreg = self._allocate_reg(insn.result_regclass, insn.result)
- insn.allocate(self)
- if DEBUG_PRINT:
- print insn
- print
- self.insns.append(insn)
- #print 'allocation done'
- #for i in self.insns:
- # print i
- #print self.var2loc
- return self.insns
+ def try_allocate_reg(self, v, selected_reg=None, need_lower_byte=False):
+ return self.rm.try_allocate_reg(v, selected_reg, need_lower_byte)
+
+ def force_allocate_reg(self, var, forbidden_vars=[], selected_reg=None,
+ need_lower_byte=False):
+ return self.rm.force_allocate_reg(var, forbidden_vars, selected_reg,
+ need_lower_byte)
+
+ def allocate_scratch_reg(self, type=INT, forbidden_vars=[], selected_reg=None):
+ assert type == INT # XXX extend this once floats are supported
+ return self.rm.allocate_scratch_reg(type=type,
+ forbidden_vars=forbidden_vars,
+ selected_reg=selected_reg)
+
+ def _check_invariants(self):
+ self.rm._check_invariants()
+
+ def loc(self, var):
+ if var.type == FLOAT:
+ assert 0, "not implemented yet"
+ return self.rm.loc(var)
+
+ def position(self):
+ return self.rm.position
+
+ def next_instruction(self):
+ self.rm.next_instruction()
+
+ def force_spill_var(self, var):
+ if var.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ self.rm.force_spill_var(var)
+
+ def before_call(self, force_store=[], save_all_regs=False):
+ self.rm.before_call(force_store, save_all_regs)
+
+ def after_call(self, v):
+ if v.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ return self.rm.after_call(v)
+
+ def call_result_location(self, v):
+ if v.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ return self.rm.call_result_location(v)
+
+ def _ensure_value_is_boxed(self, thing, forbidden_vars=[]):
+ if thing.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ return self.rm.ensure_value_is_boxed(thing, forbidden_vars)
+
+ def get_scratch_reg(self, type, forbidden_vars=[], selected_reg=None):
+ if type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ return self.rm.get_scratch_reg(type, forbidden_vars, selected_reg)
+
+ def free_temp_vars(self):
+ self.rm.free_temp_vars()
+
+ def make_sure_var_in_reg(self, var, forbidden_vars=[],
+ selected_reg=None, need_lower_byte=False):
+ if var.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ return self.rm.make_sure_var_in_reg(var, forbidden_vars,
+ selected_reg, need_lower_byte)
+
+ def convert_to_imm(self, value):
+ if isinstance(value, ConstInt):
+ return self.rm.convert_to_imm(value)
+ else:
+ assert 0, "not implemented yet"
+
+ def _sync_var(self, v):
+ if v.type == FLOAT:
+ assert 0, "not implemented yet"
+ else:
+ self.rm._sync_var(v)
+
+ # ******************************************************
+ # * P R E P A R E O P E R A T I O N S *
+ # ******************************************************
+
+
+ def void(self, op):
+ return []
+
+ prepare_int_add = prepare_binary_int_op_with_imm()
+ prepare_int_sub = prepare_binary_int_op_with_imm()
+ prepare_int_floordiv = prepare_binary_int_op_with_imm()
+
+ prepare_int_mul = prepare_binary_int_op()
+ prepare_int_mod = prepare_binary_int_op()
+ prepare_int_and = prepare_binary_int_op()
+ prepare_int_or = prepare_binary_int_op()
+ prepare_int_xor = prepare_binary_int_op()
+ prepare_int_lshift = prepare_binary_int_op()
+ prepare_int_rshift = prepare_binary_int_op()
+ prepare_uint_rshift = prepare_binary_int_op()
+ prepare_uint_floordiv = prepare_binary_int_op()
+
+ prepare_int_add_ovf = prepare_binary_int_op()
+ prepare_int_sub_ovf = prepare_binary_int_op()
+ prepare_int_mul_ovf = prepare_binary_int_op()
+
+ prepare_int_neg = prepare_unary_int_op()
+ prepare_int_invert = prepare_unary_int_op()
+
+ prepare_int_le = prepare_cmp_op()
+ prepare_int_lt = prepare_cmp_op()
+ prepare_int_ge = prepare_cmp_op()
+ prepare_int_gt = prepare_cmp_op()
+ prepare_int_eq = prepare_cmp_op()
+ prepare_int_ne = prepare_cmp_op()
+
+ prepare_ptr_eq = prepare_int_eq
+ prepare_ptr_ne = prepare_int_ne
+
+ prepare_instance_ptr_eq = prepare_ptr_eq
+ prepare_instance_ptr_ne = prepare_ptr_ne
+
+ prepare_uint_lt = prepare_cmp_op()
+ prepare_uint_le = prepare_cmp_op()
+ prepare_uint_gt = prepare_cmp_op()
+ prepare_uint_ge = prepare_cmp_op()
+
+ prepare_int_is_true = prepare_unary_cmp()
+ prepare_int_is_zero = prepare_unary_cmp()
+
+ def prepare_finish(self, op):
+ args = [None] * (op.numargs() + 1)
+ for i in range(op.numargs()):
+ arg = op.getarg(i)
+ if arg:
+ args[i] = self.loc(arg)
+ self.possibly_free_var(arg)
+ n = self.cpu.get_fail_descr_number(op.getdescr())
+ args[-1] = imm(n)
+ return args
+
+ def prepare_call_malloc_gc(self, op):
+ args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
+ return args
+
+ def _prepare_guard(self, op, args=None):
+ if args is None:
+ args = []
+ args.append(imm(len(self.frame_manager.used)))
+ for arg in op.getfailargs():
+ if arg:
+ args.append(self.loc(arg))
+ else:
+ args.append(None)
+ return args
+
+ def prepare_guard_true(self, op):
+ l0 = self._ensure_value_is_boxed(op.getarg(0))
+ args = self._prepare_guard(op, [l0])
+ return args
+
+ prepare_guard_false = prepare_guard_true
+ prepare_guard_nonnull = prepare_guard_true
+ prepare_guard_isnull = prepare_guard_true
+
+ def prepare_guard_no_overflow(self, op):
+ locs = self._prepare_guard(op)
+ self.possibly_free_vars(op.getfailargs())
+ return locs
+
+ prepare_guard_overflow = prepare_guard_no_overflow
+ prepare_guard_not_invalidated = prepare_guard_no_overflow
+
+ def prepare_guard_exception(self, op):
+ boxes = list(op.getarglist())
+ arg0 = ConstInt(rffi.cast(lltype.Signed, op.getarg(0).getint()))
+ loc = self._ensure_value_is_boxed(arg0)
+ loc1 = self.get_scratch_reg(INT, boxes)
+ if op.result in self.longevity:
+ resloc = self.force_allocate_reg(op.result, boxes)
+ self.possibly_free_var(op.result)
+ else:
+ resloc = None
+ pos_exc_value = imm(self.cpu.pos_exc_value())
+ pos_exception = imm(self.cpu.pos_exception())
+ arglocs = self._prepare_guard(op,
+ [loc, loc1, resloc, pos_exc_value, pos_exception])
+ return arglocs
+
+ def prepare_guard_no_exception(self, op):
+ loc = self._ensure_value_is_boxed(
+ ConstInt(self.cpu.pos_exception()))
+ arglocs = self._prepare_guard(op, [loc])
+ return arglocs
+
+ def prepare_guard_value(self, op):
+ boxes = list(op.getarglist())
+ a0, a1 = boxes
+ l0 = self._ensure_value_is_boxed(a0, boxes)
+ l1 = self._ensure_value_is_boxed(a1, boxes)
+ assert op.result is None
+ arglocs = self._prepare_guard(op, [l0, l1])
+ self.possibly_free_vars(op.getarglist())
+ self.possibly_free_vars(op.getfailargs())
+ return arglocs
+
+ def prepare_guard_class(self, op):
+ assert isinstance(op.getarg(0), Box)
+ boxes = list(op.getarglist())
+ x = self._ensure_value_is_boxed(boxes[0], boxes)
+ y = self.get_scratch_reg(REF, forbidden_vars=boxes)
+ y_val = rffi.cast(lltype.Signed, op.getarg(1).getint())
+ self.assembler.load(y, imm(y_val))
+ offset = self.cpu.vtable_offset
+ assert offset is not None
+ offset_loc = self._ensure_value_is_boxed(ConstInt(offset), boxes)
+ arglocs = self._prepare_guard(op, [x, y, offset_loc])
+ return arglocs
+
+ prepare_guard_nonnull_class = prepare_guard_class
+
+ def compute_hint_frame_locations(self, operations):
+ # optimization only: fill in the 'hint_frame_locations' dictionary
+ # of rm and xrm based on the JUMP at the end of the loop, by looking
+ # at where we would like the boxes to be after the jump.
+ op = operations[-1]
+ if op.getopnum() != rop.JUMP:
+ return
+ self.final_jump_op = op
+ descr = op.getdescr()
+ assert isinstance(descr, TargetToken)
+ if descr._ppc_loop_code != 0:
+ # if the target LABEL was already compiled, i.e. if it belongs
+ # to some already-compiled piece of code
+ self._compute_hint_frame_locations_from_descr(descr)
+ #else:
+ # The loop ends in a JUMP going back to a LABEL in the same loop.
+ # We cannot fill 'hint_frame_locations' immediately, but we can
+ # wait until the corresponding prepare_op_label() to know where the
+ # we would like the boxes to be after the jump.
+
+ def _compute_hint_frame_locations_from_descr(self, descr):
+ arglocs = self.assembler.target_arglocs(descr)
+ jump_op = self.final_jump_op
+ assert len(arglocs) == jump_op.numargs()
+ for i in range(jump_op.numargs()):
+ box = jump_op.getarg(i)
+ if isinstance(box, Box):
+ loc = arglocs[i]
+ if loc is not None and loc.is_stack():
+ self.frame_manager.hint_frame_locations[box] = loc
+
+ def prepare_guard_call_release_gil(self, op, guard_op):
+ # first, close the stack in the sense of the asmgcc GC root tracker
+ gcrootmap = self.cpu.gc_ll_descr.gcrootmap
+ if gcrootmap:
+ arglocs = []
+ argboxes = []
+ for i in range(op.numargs()):
+ loc, box = self._ensure_value_is_boxed(op.getarg(i), argboxes)
+ arglocs.append(loc)
+ argboxes.append(box)
+ self.assembler.call_release_gil(gcrootmap, arglocs, fcond)
+ self.possibly_free_vars(argboxes)
+ # do the call
+ faildescr = guard_op.getdescr()
+ fail_index = self.cpu.get_fail_descr_number(faildescr)
+ self.assembler._write_fail_index(fail_index)
+ args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
+ self.assembler.emit_call(op, args, self, fail_index)
+ # then reopen the stack
+ if gcrootmap:
+ self.assembler.call_reacquire_gil(gcrootmap, r.r0, fcond)
+ locs = self._prepare_guard(guard_op)
+ self.possibly_free_vars(guard_op.getfailargs())
+ return locs
+
+ def prepare_jump(self, op):
+ descr = op.getdescr()
+ assert isinstance(descr, TargetToken)
+ self.jump_target_descr = descr
+ arglocs = self.assembler.target_arglocs(descr)
+
+ # get temporary locs
+ tmploc = r.SCRATCH
+
+ # Part about non-floats
+ src_locations1 = []
+ dst_locations1 = []
+
+ # Build the four lists
+ for i in range(op.numargs()):
+ box = op.getarg(i)
+ src_loc = self.loc(box)
+ dst_loc = arglocs[i]
+ if box.type != FLOAT:
+ src_locations1.append(src_loc)
+ dst_locations1.append(dst_loc)
+ else:
+ assert 0, "not implemented yet"
+
+ remap_frame_layout(self.assembler, src_locations1,
+ dst_locations1, tmploc)
+ return []
+
+ def prepare_setfield_gc(self, op):
+ boxes = list(op.getarglist())
+ a0, a1 = boxes
+ ofs, size, sign = unpack_fielddescr(op.getdescr())
+ base_loc = self._ensure_value_is_boxed(a0, boxes)
+ value_loc = self._ensure_value_is_boxed(a1, boxes)
+ if _check_imm_arg(ofs):
+ ofs_loc = imm(ofs)
+ else:
+ ofs_loc = self.get_scratch_reg(INT, boxes)
+ self.assembler.load(ofs_loc, imm(ofs))
+ return [value_loc, base_loc, ofs_loc, imm(size)]
+
+ prepare_setfield_raw = prepare_setfield_gc
+
+ def prepare_getfield_gc(self, op):
+ a0 = op.getarg(0)
+ ofs, size, sign = unpack_fielddescr(op.getdescr())
+ base_loc = self._ensure_value_is_boxed(a0)
+ immofs = imm(ofs)
+ if _check_imm_arg(ofs):
+ ofs_loc = immofs
+ else:
+ ofs_loc = self.get_scratch_reg(INT, [a0])
+ self.assembler.load(ofs_loc, immofs)
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+ return [base_loc, ofs_loc, res, imm(size)]
+
+ prepare_getfield_raw = prepare_getfield_gc
+ prepare_getfield_raw_pure = prepare_getfield_gc
+ prepare_getfield_gc_pure = prepare_getfield_gc
+
+ def prepare_getinteriorfield_gc(self, op):
+ t = unpack_interiorfielddescr(op.getdescr())
+ ofs, itemsize, fieldsize, sign = t
+ args = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(op.getarg(0), args)
+ index_loc = self._ensure_value_is_boxed(op.getarg(1), args)
+ c_ofs = ConstInt(ofs)
+ if _check_imm_arg(c_ofs):
+ ofs_loc = imm(ofs)
+ else:
+ ofs_loc = self._ensure_value_is_boxed(c_ofs, args)
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ result_loc = self.force_allocate_reg(op.result)
+ self.possibly_free_var(op.result)
+ return [base_loc, index_loc, result_loc, ofs_loc, imm(ofs),
+ imm(itemsize), imm(fieldsize)]
+
+ def prepare_setinteriorfield_gc(self, op):
+ t = unpack_interiorfielddescr(op.getdescr())
+ ofs, itemsize, fieldsize, sign = t
+ args = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(op.getarg(0), args)
+ index_loc = self._ensure_value_is_boxed(op.getarg(1), args)
+ value_loc = self._ensure_value_is_boxed(op.getarg(2), args)
+ c_ofs = ConstInt(ofs)
+ if _check_imm_arg(c_ofs):
+ ofs_loc = imm(ofs)
+ else:
+ ofs_loc = self._ensure_value_is_boxed(c_ofs, args)
+ return [base_loc, index_loc, value_loc, ofs_loc, imm(ofs),
+ imm(itemsize), imm(fieldsize)]
+
+ def prepare_arraylen_gc(self, op):
+ arraydescr = op.getdescr()
+ assert isinstance(arraydescr, ArrayDescr)
+ ofs = arraydescr.lendescr.offset
+ arg = op.getarg(0)
+ base_loc = self._ensure_value_is_boxed(arg)
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+ return [res, base_loc, imm(ofs)]
+
+ def prepare_setarrayitem_gc(self, op):
+ size, ofs, _ = unpack_arraydescr(op.getdescr())
+ scale = get_scale(size)
+ args = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(args[0], args)
+ ofs_loc = self._ensure_value_is_boxed(args[1], args)
+ value_loc = self._ensure_value_is_boxed(args[2], args)
+ scratch_loc = self.rm.get_scratch_reg(INT,
+ [base_loc, ofs_loc, value_loc])
+ assert _check_imm_arg(ofs)
+ return [value_loc, base_loc, ofs_loc, scratch_loc, imm(scale), imm(ofs)]
+ prepare_setarrayitem_raw = prepare_setarrayitem_gc
+
+ def prepare_getarrayitem_gc(self, op):
+ boxes = op.getarglist()
+ size, ofs, _ = unpack_arraydescr(op.getdescr())
+ scale = get_scale(size)
+ base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
+ ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
+ scratch_loc = self.rm.get_scratch_reg(INT, [base_loc, ofs_loc])
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+ assert _check_imm_arg(ofs)
+ return [res, base_loc, ofs_loc, scratch_loc, imm(scale), imm(ofs)]
+
+ prepare_getarrayitem_raw = prepare_getarrayitem_gc
+ prepare_getarrayitem_gc_pure = prepare_getarrayitem_gc
+
+ def prepare_strlen(self, op):
+ args = op.getarglist()
+ l0 = self._ensure_value_is_boxed(op.getarg(0))
+ basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
+ self.cpu.translate_support_code)
+ immofs = imm(ofs_length)
+ if _check_imm_arg(ofs_length):
+ l1 = immofs
+ else:
+ l1 = self.get_scratch_reg(INT, args)
+ self.assembler.load(l1, immofs)
+
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+
+ res = self.force_allocate_reg(op.result)
+ self.possibly_free_var(op.result)
+ return [l0, l1, res]
+
+ def prepare_strgetitem(self, op):
+ boxes = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(boxes[0])
+
+ a1 = boxes[1]
+ ofs_loc = self._ensure_value_is_boxed(a1, boxes)
+
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+
+ basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
+ self.cpu.translate_support_code)
+ assert itemsize == 1
+ return [res, base_loc, ofs_loc, imm(basesize)]
+
+ def prepare_strsetitem(self, op):
+ boxes = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
+ ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
+ value_loc = self._ensure_value_is_boxed(boxes[2], boxes)
+ basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
+ self.cpu.translate_support_code)
+ assert itemsize == 1
+ return [value_loc, base_loc, ofs_loc, imm(basesize)]
+
+ prepare_copystrcontent = void
+ prepare_copyunicodecontent = void
+
+ def prepare_unicodelen(self, op):
+ l0 = self._ensure_value_is_boxed(op.getarg(0))
+ basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
+ self.cpu.translate_support_code)
+ immofs = imm(ofs_length)
+ if _check_imm_arg(ofs_length):
+ l1 = immofs
+ else:
+ l1 = self.get_scratch_reg(INT, [op.getarg(0)])
+ self.assembler.load(l1, immofs)
+
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+ return [l0, l1, res]
+
+ def prepare_unicodegetitem(self, op):
+ boxes = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
+ ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
+
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ res = self.force_allocate_reg(op.result)
+
+ basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
+ self.cpu.translate_support_code)
+ scale = itemsize / 2
+ return [res, base_loc, ofs_loc,
+ imm(scale), imm(basesize), imm(itemsize)]
+
+ def prepare_unicodesetitem(self, op):
+ boxes = op.getarglist()
+ base_loc = self._ensure_value_is_boxed(boxes[0], boxes)
+ ofs_loc = self._ensure_value_is_boxed(boxes[1], boxes)
+ value_loc = self._ensure_value_is_boxed(boxes[2], boxes)
+ basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
+ self.cpu.translate_support_code)
+ scale = itemsize / 2
+ return [value_loc, base_loc, ofs_loc,
+ imm(scale), imm(basesize), imm(itemsize)]
+
+ def prepare_same_as(self, op):
+ arg = op.getarg(0)
+ argloc = self._ensure_value_is_boxed(arg)
+ self.possibly_free_vars_for_op(op)
+ self.free_temp_vars()
+ resloc = self.force_allocate_reg(op.result)
+ return [argloc, resloc]
+
+ prepare_cast_ptr_to_int = prepare_same_as
+ prepare_cast_int_to_ptr = prepare_same_as
+
+ def prepare_call(self, op):
+ effectinfo = op.getdescr().get_extra_info()
+ if effectinfo is not None:
+ oopspecindex = effectinfo.oopspecindex
+ if oopspecindex == EffectInfo.OS_MATH_SQRT:
+ args = self.prepare_op_math_sqrt(op, fcond)
+ self.assembler.emit_op_math_sqrt(op, args, self, fcond)
+ return
+ args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
+ return args
+
+ prepare_debug_merge_point = void
+ prepare_jit_debug = void
+
+ def prepare_cond_call_gc_wb(self, op):
+ assert op.result is None
+ N = op.numargs()
+ # we force all arguments in a reg (unless they are Consts),
+ # because it will be needed anyway by the following setfield_gc
+ # or setarrayitem_gc. It avoids loading it twice from the memory.
+ arglocs = []
+ argboxes = []
+ for i in range(N):
+ loc = self._ensure_value_is_boxed(op.getarg(i), argboxes)
+ arglocs.append(loc)
+ self.rm.possibly_free_vars(argboxes)
+ return arglocs
+
+ prepare_cond_call_gc_wb_array = prepare_cond_call_gc_wb
+
+ def prepare_force_token(self, op):
+ res_loc = self.force_allocate_reg(op.result)
+ self.possibly_free_var(op.result)
+ return [res_loc]
+
+ def prepare_label(self, op):
+ # XXX big refactoring needed?
+ descr = op.getdescr()
+ assert isinstance(descr, TargetToken)
+ inputargs = op.getarglist()
+ arglocs = [None] * len(inputargs)
+ #
+ # we use force_spill() on the boxes that are not going to be really
+ # used any more in the loop, but that are kept alive anyway
+ # by being in a next LABEL's or a JUMP's argument or fail_args
+ # of some guard
+ position = self.rm.position
+ for arg in inputargs:
+ assert isinstance(arg, Box)
+ if self.last_real_usage.get(arg, -1) <= position:
+ self.force_spill_var(arg)
+
+ #
+ for i in range(len(inputargs)):
+ arg = inputargs[i]
+ assert isinstance(arg, Box)
+ loc = self.loc(arg)
+ arglocs[i] = loc
+ if loc.is_reg():
+ self.frame_manager.mark_as_free(arg)
+ #
+ descr._ppc_arglocs = arglocs
+ descr._ppc_loop_code = self.assembler.mc.currpos()
+ descr._ppc_clt = self.assembler.current_clt
+ self.assembler.target_tokens_currently_compiling[descr] = None
+ self.possibly_free_vars_for_op(op)
+ #
+ # if the LABEL's descr is precisely the target of the JUMP at the
+ # end of the same loop, i.e. if what we are compiling is a single
+ # loop that ends up jumping to this LABEL, then we can now provide
+ # the hints about the expected position of the spilled variables.
+ jump_op = self.final_jump_op
+ if jump_op is not None and jump_op.getdescr() is descr:
+ self._compute_hint_frame_locations_from_descr(descr)
+
+ def prepare_guard_call_may_force(self, op, guard_op):
+ faildescr = guard_op.getdescr()
+ fail_index = self.cpu.get_fail_descr_number(faildescr)
+ self.assembler._write_fail_index(fail_index)
+ args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
+ for v in guard_op.getfailargs():
+ if v in self.rm.reg_bindings:
+ self.force_spill_var(v)
+ self.assembler.emit_call(op, args, self, fail_index)
+ locs = self._prepare_guard(guard_op)
+ self.possibly_free_vars(guard_op.getfailargs())
+ return locs
+
+ def prepare_guard_call_assembler(self, op, guard_op):
+ descr = op.getdescr()
+ assert isinstance(descr, JitCellToken)
+ jd = descr.outermost_jitdriver_sd
+ assert jd is not None
+ #size = jd.portal_calldescr.get_result_size(self.cpu.translate_support_code)
+ size = jd.portal_calldescr.get_result_size()
+ vable_index = jd.index_of_virtualizable
+ if vable_index >= 0:
+ self._sync_var(op.getarg(vable_index))
+ vable = self.frame_manager.loc(op.getarg(vable_index))
+ else:
+ vable = imm(0)
+ self.possibly_free_vars(guard_op.getfailargs())
+ return [imm(size), vable]
+
+ def _prepare_args_for_new_op(self, new_args):
+ gc_ll_descr = self.cpu.gc_ll_descr
+ args = gc_ll_descr.args_for_new(new_args)
+ arglocs = []
+ for i in range(len(args)):
+ arg = args[i]
+ t = TempInt()
+ l = self.force_allocate_reg(t, selected_reg=r.MANAGED_REGS[i])
+ self.assembler.load(l, imm(arg))
+ arglocs.append(t)
+ return arglocs
+
+ # from ../x86/regalloc.py:791
+ def _unpack_fielddescr(self, fielddescr):
+ assert isinstance(fielddescr, BaseFieldDescr)
+ ofs = fielddescr.offset
+ size = fielddescr.get_field_size(self.cpu.translate_support_code)
+ ptr = fielddescr.is_pointer_field()
+ return ofs, size, ptr
+
+ # from ../x86/regalloc.py:779
+ def _unpack_arraydescr(self, arraydescr):
+ assert isinstance(arraydescr, BaseArrayDescr)
+ cpu = self.cpu
+ ofs_length = arraydescr.get_ofs_length(cpu.translate_support_code)
+ ofs = arraydescr.get_base_size(cpu.translate_support_code)
+ size = arraydescr.get_item_size(cpu.translate_support_code)
+ ptr = arraydescr.is_array_of_pointers()
+ scale = 0
+ while (1 << scale) < size:
+ scale += 1
+ assert (1 << scale) == size
+ return size, scale, ofs, ofs_length, ptr
+
+ def prepare_force_spill(self, op):
+ self.force_spill_var(op.getarg(0))
+ return []
+
+def add_none_argument(fn):
+ return lambda self, op: fn(self, op, None)
+
+def notimplemented(self, op):
+ raise NotImplementedError, op
+
+def notimplemented_with_guard(self, op, guard_op):
+
+ raise NotImplementedError, op
+
+operations = [notimplemented] * (rop._LAST + 1)
+operations_with_guard = [notimplemented_with_guard] * (rop._LAST + 1)
+
+def get_scale(size):
+ scale = 0
+ while (1 << scale) < size:
+ scale += 1
+ assert (1 << scale) == size
+ return scale
+
+for key, value in rop.__dict__.items():
+ key = key.lower()
+ if key.startswith('_'):
+ continue
+ methname = 'prepare_%s' % key
+ if hasattr(Regalloc, methname):
+ func = getattr(Regalloc, methname).im_func
+ operations[value] = func
+
+for key, value in rop.__dict__.items():
+ key = key.lower()
+ if key.startswith('_'):
+ continue
+ methname = 'prepare_guard_%s' % key
+ if hasattr(Regalloc, methname):
+ func = getattr(Regalloc, methname).im_func
+ operations_with_guard[value] = func
+ operations[value] = add_none_argument(func)
+
+Regalloc.operations = operations
+Regalloc.operations_with_guard = operations_with_guard
diff --git a/pypy/jit/backend/ppc/ppcgen/register.py b/pypy/jit/backend/ppc/register.py
rename from pypy/jit/backend/ppc/ppcgen/register.py
rename to pypy/jit/backend/ppc/register.py
--- a/pypy/jit/backend/ppc/ppcgen/register.py
+++ b/pypy/jit/backend/ppc/register.py
@@ -1,5 +1,5 @@
-from pypy.jit.backend.ppc.ppcgen.locations import (RegisterLocation,
- FPRegisterLocation)
+from pypy.jit.backend.ppc.locations import (RegisterLocation,
+ FPRegisterLocation)
ALL_REGS = [RegisterLocation(i) for i in range(32)]
ALL_FLOAT_REGS = [FPRegisterLocation(i) for i in range(32)]
diff --git a/pypy/jit/backend/ppc/ppcgen/regname.py b/pypy/jit/backend/ppc/regname.py
rename from pypy/jit/backend/ppc/ppcgen/regname.py
rename to pypy/jit/backend/ppc/regname.py
diff --git a/pypy/jit/backend/ppc/rgenop.py b/pypy/jit/backend/ppc/rgenop.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/rgenop.py
+++ /dev/null
@@ -1,1427 +0,0 @@
-import py
-from pypy.jit.codegen.model import AbstractRGenOp, GenLabel, GenBuilder
-from pypy.jit.codegen.model import GenVar, GenConst, CodeGenSwitch
-from pypy.jit.codegen.model import ReplayBuilder, dummy_var
-from pypy.rpython.lltypesystem import lltype, llmemory
-from pypy.rpython.lltypesystem import lloperation
-from pypy.rpython.extfunc import register_external
-from pypy.rlib.objectmodel import specialize, we_are_translated
-from pypy.jit.codegen.conftest import option
-from ctypes import POINTER, cast, c_void_p, c_int, CFUNCTYPE
-
-from pypy.jit.codegen.ppc import codebuf
-from pypy.jit.codegen.ppc.instruction import rSP, rFP, rSCRATCH, gprs
-from pypy.jit.codegen.ppc import instruction as insn
-from pypy.jit.codegen.ppc.regalloc import RegisterAllocation
-from pypy.jit.codegen.emit_moves import emit_moves, emit_moves_safe
-
-from pypy.jit.codegen.ppc.ppcgen.rassemblermaker import make_rassembler
-from pypy.jit.codegen.ppc.ppcgen.ppc_assembler import MyPPCAssembler
-
-from pypy.jit.codegen.i386.rgenop import gc_malloc_fnaddr
-from pypy.rpython.annlowlevel import llhelper
-
-class RPPCAssembler(make_rassembler(MyPPCAssembler)):
- def emit(self, value):
- self.mc.write(value)
-
-_PPC = RPPCAssembler
-
-
-_flush_icache = None
-def flush_icache(base, size):
- global _flush_icache
- if _flush_icache == None:
- cpath = py.magic.autopath().dirpath().join('_flush_icache.c')
- _flush_icache = cpath._getpymodule()._flush_icache
- _flush_icache(base, size)
-register_external(flush_icache, [int, int], None, "LL_flush_icache")
-
-
-NSAVEDREGISTERS = 19
-
-DEBUG_TRAP = option.trap
-DEBUG_PRINT = option.debug_print
-
-_var_index = [0]
-class Var(GenVar):
- conditional = False
- def __init__(self):
- self.__magic_index = _var_index[0]
- _var_index[0] += 1
- def __repr__(self):
- return "v%d" % self.__magic_index
- def fits_in_uimm(self):
- return False
- def fits_in_simm(self):
- return False
-
-class ConditionVar(Var):
- """ Used for vars that originated as the result of a conditional
- operation, like a == b """
- conditional = True
-
-class IntConst(GenConst):
-
- def __init__(self, value):
- self.value = value
-
- def __repr__(self):
- return 'IntConst(%d)'%self.value
-
- @specialize.arg(1)
- def revealconst(self, T):
- if isinstance(T, lltype.Ptr):
- return lltype.cast_int_to_ptr(T, self.value)
- elif T is llmemory.Address:
- return llmemory.cast_int_to_adr(self.value)
- else:
- return lltype.cast_primitive(T, self.value)
-
- def load(self, insns, var):
- insns.append(
- insn.Insn_GPR__IMM(_PPC.load_word,
- var, [self]))
-
- def load_now(self, asm, loc):
- if loc.is_register:
- assert isinstance(loc, insn.GPR)
- asm.load_word(loc.number, self.value)
- else:
- #print 'load_now to', loc.offset
- asm.load_word(rSCRATCH, self.value)
- asm.stw(rSCRATCH, rFP, loc.offset)
-
- def fits_in_simm(self):
- return abs(self.value) < 2**15
-
- def fits_in_uimm(self):
- return 0 <= self.value < 2**16
-
-class AddrConst(GenConst):
-
- def __init__(self, addr):
- self.addr = addr
-
- @specialize.arg(1)
- def revealconst(self, T):
- if T is llmemory.Address:
- return self.addr
- elif isinstance(T, lltype.Ptr):
- return llmemory.cast_adr_to_ptr(self.addr, T)
- elif T is lltype.Signed:
- return llmemory.cast_adr_to_int(self.addr)
- else:
- assert 0, "XXX not implemented"
-
- def fits_in_simm(self):
- return False
-
- def fits_in_uimm(self):
- return False
-
- def load(self, insns, var):
- i = IntConst(llmemory.cast_adr_to_int(self.addr))
- insns.append(
- insn.Insn_GPR__IMM(RPPCAssembler.load_word,
- var, [i]))
-
- def load_now(self, asm, loc):
- value = llmemory.cast_adr_to_int(self.addr)
- if loc.is_register:
- assert isinstance(loc, insn.GPR)
- asm.load_word(loc.number, value)
- else:
- #print 'load_now to', loc.offset
- asm.load_word(rSCRATCH, value)
- asm.stw(rSCRATCH, rFP, loc.offset)
-
-
-class JumpPatchupGenerator(object):
-
- def __init__(self, insns, allocator):
- self.insns = insns
- self.allocator = allocator
-
- def emit_move(self, tarloc, srcloc):
- srcvar = None
- if DEBUG_PRINT:
- for v, loc in self.allocator.var2loc.iteritems():
- if loc is srcloc:
- srcvar = v
- break
- emit = self.insns.append
- if tarloc == srcloc:
- return
- if tarloc.is_register and srcloc.is_register:
- assert isinstance(tarloc, insn.GPR)
- if isinstance(srcloc, insn.GPR):
- emit(insn.Move(tarloc, srcloc))
- else:
- assert isinstance(srcloc, insn.CRF)
- emit(srcloc.move_to_gpr(tarloc.number))
- elif tarloc.is_register and not srcloc.is_register:
- emit(insn.Unspill(srcvar, tarloc, srcloc))
- elif not tarloc.is_register and srcloc.is_register:
- emit(insn.Spill(srcvar, srcloc, tarloc))
- elif not tarloc.is_register and not srcloc.is_register:
- emit(insn.Unspill(srcvar, insn.gprs[0], srcloc))
- emit(insn.Spill(srcvar, insn.gprs[0], tarloc))
-
- def create_fresh_location(self):
- return self.allocator.spill_slot()
-
-class StackInfo(Var):
- # not really a Var at all, but needs to be mixable with Consts....
- # offset will be assigned later
- offset = 0
- pass
-
-def prepare_for_jump(insns, sourcevars, src2loc, target, allocator):
-
- tar2src = {} # tar var -> src var
- tar2loc = {}
-
- # construct mapping of targets to sources; note that "target vars"
- # and "target locs" are the same thing right now
- targetlocs = target.arg_locations
- tarvars = []
-
-## if DEBUG_PRINT:
-## print targetlocs
-## print allocator.var2loc
-
- for i in range(len(targetlocs)):
- tloc = targetlocs[i]
- src = sourcevars[i]
- if isinstance(src, Var):
- tar2loc[tloc] = tloc
- tar2src[tloc] = src
- tarvars.append(tloc)
- if not tloc.is_register:
- if tloc in allocator.free_stack_slots:
- allocator.free_stack_slots.remove(tloc)
-
- gen = JumpPatchupGenerator(insns, allocator)
- emit_moves(gen, tarvars, tar2src, tar2loc, src2loc)
-
- for i in range(len(targetlocs)):
- tloc = targetlocs[i]
- src = sourcevars[i]
- if not isinstance(src, Var):
- insns.append(insn.Load(tloc, src))
-
-class Label(GenLabel):
-
- def __init__(self, args_gv):
- self.args_gv = args_gv
- #self.startaddr = startaddr
- #self.arg_locations = arg_locations
- self.min_stack_offset = 1
-
-# our approach to stack layout:
-
-# on function entry, the stack looks like this:
-
-# ....
-# | parameter area |
-# | linkage area | <- rSP points to the last word of the linkage area
-# +----------------+
-
-# we set things up like so:
-
-# | parameter area |
-# | linkage area | <- rFP points to where the rSP was
-# | saved registers |
-# | local variables |
-# +-----------------+ <- rSP points here, and moves around between basic blocks
-
-# points of note (as of 2006-11-09 anyway :-):
-# 1. we currently never spill to the parameter area (should fix?)
-# 2. we always save all callee-save registers
-# 3. as each basic block can move the SP around as it sees fit, we index
-# into the local variables area from the FP (frame pointer; it is not
-# usual on the PPC to have a frame pointer, but there's no reason we
-# can't have one :-)
-
-
-class Builder(GenBuilder):
-
- def __init__(self, rgenop):
- self.rgenop = rgenop
- self.asm = RPPCAssembler()
- self.asm.mc = None
- self.insns = []
- self.initial_spill_offset = 0
- self.initial_var2loc = None
- self.max_param_space = -1
- self.final_jump_addr = 0
-
- self.start = 0
- self.closed = True
- self.patch_start_here = 0
-
- # ----------------------------------------------------------------
- # the public Builder interface:
-
- def end(self):
- pass
-
- @specialize.arg(1)
- def genop1(self, opname, gv_arg):
- #print opname, 'on', id(self)
- genmethod = getattr(self, 'op_' + opname)
- r = genmethod(gv_arg)
- #print '->', id(r)
- return r
-
- @specialize.arg(1)
- def genop2(self, opname, gv_arg1, gv_arg2):
- #print opname, 'on', id(self)
- genmethod = getattr(self, 'op_' + opname)
- r = genmethod(gv_arg1, gv_arg2)
- #print '->', id(r)
- return r
-
- @specialize.arg(1)
- def genraisingop2(self, opname, gv_arg1, gv_arg2):
- genmethod = getattr(self, 'raisingop_' + opname)
- r = genmethod(gv_arg1, gv_arg2)
- return r
-
- @specialize.arg(1)
- def genraisingop1(self, opname, gv_arg):
- genmethod = getattr(self, 'raisingop_' + opname)
- r = genmethod(gv_arg)
- return r
-
- def genop_call(self, sigtoken, gv_fnptr, args_gv):
- self.insns.append(insn.SpillCalleeSaves())
- for i in range(len(args_gv)):
- self.insns.append(insn.LoadArg(i, args_gv[i]))
- gv_result = Var()
- self.max_param_space = max(self.max_param_space, len(args_gv)*4)
- self.insns.append(insn.CALL(gv_result, gv_fnptr))
- return gv_result
-
- def genop_getfield(self, fieldtoken, gv_ptr):
- fieldoffset, fieldsize = fieldtoken
- opcode = {1:_PPC.lbz, 2:_PPC.lhz, 4:_PPC.lwz}[fieldsize]
- return self._arg_simm_op(gv_ptr, IntConst(fieldoffset), opcode)
-
- def genop_setfield(self, fieldtoken, gv_ptr, gv_value):
- gv_result = Var()
- fieldoffset, fieldsize = fieldtoken
- opcode = {1:_PPC.stb, 2:_PPC.sth, 4:_PPC.stw}[fieldsize]
- self.insns.append(
- insn.Insn_None__GPR_GPR_IMM(opcode,
- [gv_value, gv_ptr, IntConst(fieldoffset)]))
- return gv_result
-
- def genop_getsubstruct(self, fieldtoken, gv_ptr):
- return self._arg_simm_op(gv_ptr, IntConst(fieldtoken[0]), _PPC.addi)
-
- def genop_getarrayitem(self, arraytoken, gv_ptr, gv_index):
- _, _, itemsize = arraytoken
- opcode = {1:_PPC.lbzx,
- 2:_PPC.lhzx,
- 4:_PPC.lwzx}[itemsize]
- opcodei = {1:_PPC.lbz,
- 2:_PPC.lhz,
- 4:_PPC.lwz}[itemsize]
- gv_itemoffset = self.itemoffset(arraytoken, gv_index)
- return self._arg_arg_op_with_simm(gv_ptr, gv_itemoffset, opcode, opcodei)
-
- def genop_getarraysubstruct(self, arraytoken, gv_ptr, gv_index):
- _, _, itemsize = arraytoken
- assert itemsize == 4
- gv_itemoffset = self.itemoffset(arraytoken, gv_index)
- return self._arg_arg_op_with_simm(gv_ptr, gv_itemoffset, _PPC.add, _PPC.addi,
- commutative=True)
-
- def genop_getarraysize(self, arraytoken, gv_ptr):
- lengthoffset, _, _ = arraytoken
- return self._arg_simm_op(gv_ptr, IntConst(lengthoffset), _PPC.lwz)
-
- def genop_setarrayitem(self, arraytoken, gv_ptr, gv_index, gv_value):
- _, _, itemsize = arraytoken
- gv_itemoffset = self.itemoffset(arraytoken, gv_index)
- gv_result = Var()
- if gv_itemoffset.fits_in_simm():
- opcode = {1:_PPC.stb,
- 2:_PPC.sth,
- 4:_PPC.stw}[itemsize]
- self.insns.append(
- insn.Insn_None__GPR_GPR_IMM(opcode,
- [gv_value, gv_ptr, gv_itemoffset]))
- else:
- opcode = {1:_PPC.stbx,
- 2:_PPC.sthx,
- 4:_PPC.stwx}[itemsize]
- self.insns.append(
- insn.Insn_None__GPR_GPR_GPR(opcode,
- [gv_value, gv_ptr, gv_itemoffset]))
-
- def genop_malloc_fixedsize(self, alloctoken):
- return self.genop_call(1, # COUGH
- IntConst(gc_malloc_fnaddr()),
- [IntConst(alloctoken)])
-
- def genop_malloc_varsize(self, varsizealloctoken, gv_size):
- gv_itemoffset = self.itemoffset(varsizealloctoken, gv_size)
- gv_result = self.genop_call(1, # COUGH
- IntConst(gc_malloc_fnaddr()),
- [gv_itemoffset])
- lengthoffset, _, _ = varsizealloctoken
- self.insns.append(
- insn.Insn_None__GPR_GPR_IMM(_PPC.stw,
- [gv_size, gv_result, IntConst(lengthoffset)]))
- return gv_result
-
- def genop_same_as(self, gv_arg):
- if not isinstance(gv_arg, Var):
- gv_result = Var()
- gv_arg.load(self.insns, gv_result)
- return gv_result
- else:
- return gv_arg
-
- def genop_cast_int_to_ptr(self, kind, gv_int):
- return gv_int
-
-## def genop_debug_pdb(self): # may take an args_gv later
-
- def genop_get_frame_base(self):
- gv_result = Var()
- self.insns.append(
- insn.LoadFramePointer(gv_result))
- return gv_result
-
- def get_frame_info(self, vars_gv):
- result = []
- for v in vars_gv:
- if isinstance(v, Var):
- place = StackInfo()
- self.insns.append(insn.CopyIntoStack(place, v))
- result.append(place)
- else:
- result.append(None)
- return result
-
- def alloc_frame_place(self, kind, gv_initial_value=None):
- place = StackInfo()
- if gv_initial_value is None:
- gv_initial_value = AddrConst(llmemory.NULL)
- self.insns.append(insn.CopyIntoStack(place, gv_initial_value))
- return place
-
- def genop_absorb_place(self, place):
- var = Var()
- self.insns.append(insn.CopyOffStack(var, place))
- return var
-
- def enter_next_block(self, args_gv):
- if DEBUG_PRINT:
- print 'enter_next_block1', args_gv
- seen = {}
- for i in range(len(args_gv)):
- gv = args_gv[i]
- if isinstance(gv, Var):
- if gv in seen:
- new_gv = self._arg_op(gv, _PPC.mr)
- args_gv[i] = new_gv
- seen[gv] = True
- else:
- new_gv = Var()
- gv.load(self.insns, new_gv)
- args_gv[i] = new_gv
-
- if DEBUG_PRINT:
- print 'enter_next_block2', args_gv
-
- r = Label(args_gv)
- self.insns.append(insn.Label(r))
- return r
-
- def jump_if_false(self, gv_condition, args_gv):
- return self._jump(gv_condition, False, args_gv)
-
- def jump_if_true(self, gv_condition, args_gv):
- return self._jump(gv_condition, True, args_gv)
-
- def finish_and_return(self, sigtoken, gv_returnvar):
- self.insns.append(insn.Return(gv_returnvar))
- self.allocate_and_emit([])
-
- # standard epilogue:
-
- # restore old SP
- self.asm.lwz(rSP, rSP, 0)
- # restore all callee-save GPRs
- self.asm.lmw(gprs[32-NSAVEDREGISTERS].number, rSP, -4*(NSAVEDREGISTERS+1))
- # restore Condition Register
- self.asm.lwz(rSCRATCH, rSP, 4)
- self.asm.mtcr(rSCRATCH)
- # restore Link Register and jump to it
- self.asm.lwz(rSCRATCH, rSP, 8)
- self.asm.mtlr(rSCRATCH)
- self.asm.blr()
-
- self._close()
-
- def finish_and_goto(self, outputargs_gv, target):
- if target.min_stack_offset == 1:
- self.pause_writing(outputargs_gv)
- self.start_writing()
- allocator = self.allocate(outputargs_gv)
- if DEBUG_PRINT:
- before_moves = len(self.insns)
- print outputargs_gv
- print target.args_gv
- allocator.spill_offset = min(allocator.spill_offset, target.min_stack_offset)
- prepare_for_jump(
- self.insns, outputargs_gv, allocator.var2loc, target, allocator)
- if DEBUG_PRINT:
- print 'moves:'
- for i in self.insns[before_moves:]:
- print ' ', i
- self.emit(allocator)
- here_size = self._stack_size(allocator.spill_offset)
- there_size = self._stack_size(target.min_stack_offset)
- if here_size != there_size:
- self.emit_stack_adjustment(there_size)
- if self.rgenop.DEBUG_SCRIBBLE:
- if here_size > there_size:
- offsets = range(there_size, here_size, 4)
- else:
- offsets = range(here_size, there_size, 4)
- for offset in offsets:
- self.asm.load_word(rSCRATCH, 0x23456789)
- self.asm.stw(rSCRATCH, rSP, -offset)
- self.asm.load_word(rSCRATCH, target.startaddr)
- self.asm.mtctr(rSCRATCH)
- self.asm.bctr()
- self._close()
-
- def flexswitch(self, gv_exitswitch, args_gv):
- # make sure the exitswitch ends the block in a register:
- crresult = Var()
- self.insns.append(insn.FakeUse(crresult, gv_exitswitch))
- allocator = self.allocate_and_emit(args_gv)
- switch_mc = self.asm.mc.reserve(7 * 5 + 4)
- self._close()
- result = FlexSwitch(self.rgenop, switch_mc,
- allocator.loc_of(gv_exitswitch),
- allocator.loc_of(crresult),
- allocator.var2loc,
- allocator.spill_offset)
- return result, result.add_default()
-
- def start_writing(self):
- if not self.closed:
- return self
- assert self.asm.mc is None
- if self.final_jump_addr != 0:
- mc = self.rgenop.open_mc()
- target = mc.tell()
- if target == self.final_jump_addr + 16:
- mc.setpos(mc.getpos()-4)
- else:
- self.asm.mc = self.rgenop.ExistingCodeBlock(
- self.final_jump_addr, self.final_jump_addr+8)
- self.asm.load_word(rSCRATCH, target)
- flush_icache(self.final_jump_addr, 8)
- self._code_start = mc.tell()
- self.asm.mc = mc
- self.final_jump_addr = 0
- self.closed = False
- return self
- else:
- self._open()
- self.maybe_patch_start_here()
- return self
-
- def maybe_patch_start_here(self):
- if self.patch_start_here:
- mc = self.asm.mc
- self.asm.mc = self.rgenop.ExistingCodeBlock(
- self.patch_start_here, self.patch_start_here+8)
- self.asm.load_word(rSCRATCH, mc.tell())
- flush_icache(self.patch_start_here, 8)
- self.asm.mc = mc
- self.patch_start_here = 0
-
- def pause_writing(self, args_gv):
- allocator = self.allocate_and_emit(args_gv)
- self.initial_var2loc = allocator.var2loc
- self.initial_spill_offset = allocator.spill_offset
- self.insns = []
- self.max_param_space = -1
- self.final_jump_addr = self.asm.mc.tell()
- self.closed = True
- self.asm.nop()
- self.asm.nop()
- self.asm.mtctr(rSCRATCH)
- self.asm.bctr()
- self._close()
- return self
-
- # ----------------------------------------------------------------
- # ppc-specific interface:
-
- def itemoffset(self, arraytoken, gv_index):
- # if gv_index is constant, this can return a constant...
- lengthoffset, startoffset, itemsize = arraytoken
-
- gv_offset = Var()
- self.insns.append(
- insn.Insn_GPR__GPR_IMM(RPPCAssembler.mulli,
- gv_offset, [gv_index, IntConst(itemsize)]))
- gv_itemoffset = Var()
- self.insns.append(
- insn.Insn_GPR__GPR_IMM(RPPCAssembler.addi,
- gv_itemoffset, [gv_offset, IntConst(startoffset)]))
- return gv_itemoffset
-
- def _write_prologue(self, sigtoken):
- numargs = sigtoken # for now
- if DEBUG_TRAP:
- self.asm.trap()
- inputargs = [Var() for i in range(numargs)]
- assert self.initial_var2loc is None
- self.initial_var2loc = {}
- for arg in inputargs[:8]:
- self.initial_var2loc[arg] = gprs[3+len(self.initial_var2loc)]
- if len(inputargs) > 8:
- for i in range(8, len(inputargs)):
- arg = inputargs[i]
- self.initial_var2loc[arg] = insn.stack_slot(24 + 4 * len(self.initial_var2loc))
- self.initial_spill_offset = self._var_offset(0)
-
- # Standard prologue:
-
- # Minimum stack space = 24+params+lv+4*GPRSAVE+8*FPRSAVE
- # params = stack space for parameters for functions we call
- # lv = stack space for local variables
- # GPRSAVE = the number of callee-save GPRs we save, currently
- # NSAVEDREGISTERS which is 19, i.e. all of them
- # FPRSAVE = the number of callee-save FPRs we save, currently 0
- # Initially, we set params == lv == 0 and allow each basic block to
- # ensure it has enough space to continue.
-
- minspace = self._stack_size(self._var_offset(0))
- # save Link Register
- self.asm.mflr(rSCRATCH)
- self.asm.stw(rSCRATCH, rSP, 8)
- # save Condition Register
- self.asm.mfcr(rSCRATCH)
- self.asm.stw(rSCRATCH, rSP, 4)
- # save the callee-save GPRs
- self.asm.stmw(gprs[32-NSAVEDREGISTERS].number, rSP, -4*(NSAVEDREGISTERS + 1))
- # set up frame pointer
- self.asm.mr(rFP, rSP)
- # save stack pointer into linkage area and set stack pointer for us.
- self.asm.stwu(rSP, rSP, -minspace)
-
- if self.rgenop.DEBUG_SCRIBBLE:
- # write junk into all non-argument, non rFP or rSP registers
- self.asm.load_word(rSCRATCH, 0x12345678)
- for i in range(min(11, 3+len(self.initial_var2loc)), 32):
- self.asm.load_word(i, 0x12345678)
- # scribble the part of the stack between
- # self._var_offset(0) and minspace
- for offset in range(self._var_offset(0), -minspace, -4):
- self.asm.stw(rSCRATCH, rFP, offset)
- # and then a bit more
- for offset in range(-minspace-4, -minspace-200, -4):
- self.asm.stw(rSCRATCH, rFP, offset)
-
- return inputargs
-
- def _var_offset(self, v):
- """v represents an offset into the local variable area in bytes;
- this returns the offset relative to rFP"""
- return -(4*NSAVEDREGISTERS+4+v)
-
- def _stack_size(self, lv):
- """ Returns the required stack size to store all data, assuming
- that there are 'param' bytes of parameters for callee functions and
- 'lv' is the largest (wrt to abs() :) rFP-relative byte offset of
- any variable on the stack. Plus 4 because the rFP actually points
- into our caller's linkage area."""
- assert lv <= 0
- if self.max_param_space >= 0:
- param = max(self.max_param_space, 32) + 24
- else:
- param = 0
- return ((4 + param - lv + 15) & ~15)
-
- def _open(self):
- self.asm.mc = self.rgenop.open_mc()
- self._code_start = self.asm.mc.tell()
- self.closed = False
-
- def _close(self):
- _code_stop = self.asm.mc.tell()
- code_size = _code_stop - self._code_start
- flush_icache(self._code_start, code_size)
- self.rgenop.close_mc(self.asm.mc)
- self.asm.mc = None
-
- def allocate_and_emit(self, live_vars_gv):
- allocator = self.allocate(live_vars_gv)
- return self.emit(allocator)
-
- def allocate(self, live_vars_gv):
- assert self.initial_var2loc is not None
- allocator = RegisterAllocation(
- self.rgenop.freeregs,
- self.initial_var2loc,
- self.initial_spill_offset)
- self.insns = allocator.allocate_for_insns(self.insns)
- return allocator
-
- def emit(self, allocator):
- in_size = self._stack_size(self.initial_spill_offset)
- our_size = self._stack_size(allocator.spill_offset)
- if in_size != our_size:
- assert our_size > in_size
- self.emit_stack_adjustment(our_size)
- if self.rgenop.DEBUG_SCRIBBLE:
- for offset in range(in_size, our_size, 4):
- self.asm.load_word(rSCRATCH, 0x23456789)
- self.asm.stw(rSCRATCH, rSP, -offset)
- if self.rgenop.DEBUG_SCRIBBLE:
- locs = {}
- for _, loc in self.initial_var2loc.iteritems():
- locs[loc] = True
- regs = insn.gprs[3:]
- for reg in regs:
- if reg not in locs:
- self.asm.load_word(reg.number, 0x3456789)
- self.asm.load_word(0, 0x3456789)
- for offset in range(self._var_offset(0),
- self.initial_spill_offset,
- -4):
- if insn.stack_slot(offset) not in locs:
- self.asm.stw(0, rFP, offset)
- for insn_ in self.insns:
- insn_.emit(self.asm)
- for label in allocator.labels_to_tell_spill_offset_to:
- label.min_stack_offset = allocator.spill_offset
- for builder in allocator.builders_to_tell_spill_offset_to:
- builder.initial_spill_offset = allocator.spill_offset
- return allocator
-
- def emit_stack_adjustment(self, newsize):
- # the ABI requires that at all times that r1 is valid, in the
- # sense that it must point to the bottom of the stack and that
- # executing SP <- *(SP) repeatedly walks the stack.
- # this code satisfies this, although there is a 1-instruction
- # window where such walking would find a strange intermediate
- # "frame"
- self.asm.addi(rSCRATCH, rFP, -newsize)
- self.asm.sub(rSCRATCH, rSCRATCH, rSP)
-
- # this is a pure debugging check that we avoid the situation
- # where *(r1) == r1 which would violates the ABI rules listed
- # above. after a while it can be removed or maybe made
- # conditional on some --option passed to py.test
- self.asm.tweqi(rSCRATCH, 0)
-
- self.asm.stwux(rSP, rSP, rSCRATCH)
- self.asm.stw(rFP, rSP, 0)
-
- def _arg_op(self, gv_arg, opcode):
- gv_result = Var()
- self.insns.append(
- insn.Insn_GPR__GPR(opcode, gv_result, gv_arg))
- return gv_result
-
- def _arg_arg_op(self, gv_x, gv_y, opcode):
- gv_result = Var()
- self.insns.append(
- insn.Insn_GPR__GPR_GPR(opcode, gv_result, [gv_x, gv_y]))
- return gv_result
-
- def _arg_simm_op(self, gv_x, gv_imm, opcode):
- assert gv_imm.fits_in_simm()
- gv_result = Var()
- self.insns.append(
- insn.Insn_GPR__GPR_IMM(opcode, gv_result, [gv_x, gv_imm]))
- return gv_result
-
- def _arg_uimm_op(self, gv_x, gv_imm, opcode):
- assert gv_imm.fits_in_uimm()
- gv_result = Var()
- self.insns.append(
- insn.Insn_GPR__GPR_IMM(opcode, gv_result, [gv_x, gv_imm]))
- return gv_result
-
- def _arg_arg_op_with_simm(self, gv_x, gv_y, opcode, opcodei,
- commutative=False):
- if gv_y.fits_in_simm():
- return self._arg_simm_op(gv_x, gv_y, opcodei)
- elif gv_x.fits_in_simm() and commutative:
- return self._arg_simm_op(gv_y, gv_x, opcodei)
- else:
- return self._arg_arg_op(gv_x, gv_y, opcode)
-
- def _arg_arg_op_with_uimm(self, gv_x, gv_y, opcode, opcodei,
- commutative=False):
- if gv_y.fits_in_uimm():
- return self._arg_uimm_op(gv_x, gv_y, opcodei)
- elif gv_x.fits_in_uimm() and commutative:
- return self._arg_uimm_op(gv_y, gv_x, opcodei)
- else:
- return self._arg_arg_op(gv_x, gv_y, opcode)
-
- def _identity(self, gv_arg):
- return gv_arg
-
- cmp2info = {
- # bit-in-crf negated
- 'gt': ( 1, 0 ),
- 'lt': ( 0, 0 ),
- 'le': ( 1, 1 ),
- 'ge': ( 0, 1 ),
- 'eq': ( 2, 0 ),
- 'ne': ( 2, 1 ),
- }
-
- cmp2info_flipped = {
- # bit-in-crf negated
- 'gt': ( 0, 0 ),
- 'lt': ( 1, 0 ),
- 'le': ( 0, 1 ),
- 'ge': ( 1, 1 ),
- 'eq': ( 2, 0 ),
- 'ne': ( 2, 1 ),
- }
-
- def _compare(self, op, gv_x, gv_y):
- #print "op", op
- gv_result = ConditionVar()
- if gv_y.fits_in_simm():
- self.insns.append(
- insn.CMPWI(self.cmp2info[op], gv_result, [gv_x, gv_y]))
- elif gv_x.fits_in_simm():
- self.insns.append(
- insn.CMPWI(self.cmp2info_flipped[op], gv_result, [gv_y, gv_x]))
- else:
- self.insns.append(
- insn.CMPW(self.cmp2info[op], gv_result, [gv_x, gv_y]))
- return gv_result
-
- def _compare_u(self, op, gv_x, gv_y):
- gv_result = ConditionVar()
- if gv_y.fits_in_uimm():
- self.insns.append(
- insn.CMPWLI(self.cmp2info[op], gv_result, [gv_x, gv_y]))
- elif gv_x.fits_in_uimm():
- self.insns.append(
- insn.CMPWLI(self.cmp2info_flipped[op], gv_result, [gv_y, gv_x]))
- else:
- self.insns.append(
- insn.CMPWL(self.cmp2info[op], gv_result, [gv_x, gv_y]))
- return gv_result
-
- def _jump(self, gv_condition, if_true, args_gv):
- targetbuilder = self.rgenop.newbuilder()
-
- self.insns.append(
- insn.Jump(gv_condition, targetbuilder, if_true, args_gv))
-
- return targetbuilder
-
- def _ov(self):
- # mfxer rFOO
- # extrwi rBAR, rFOO, 1, 1
- gv_xer = Var()
- self.insns.append(
- insn.Insn_GPR(_PPC.mfxer, gv_xer))
- gv_ov = Var()
- self.insns.append(insn.Extrwi(gv_ov, gv_xer, 1, 1))
- return gv_ov
-
- def op_bool_not(self, gv_arg):
- return self._arg_uimm_op(gv_arg, self.rgenop.genconst(1), RPPCAssembler.xori)
-
- def op_int_is_true(self, gv_arg):
- return self._compare('ne', gv_arg, self.rgenop.genconst(0))
-
- def op_int_neg(self, gv_arg):
- return self._arg_op(gv_arg, _PPC.neg)
-
- def raisingop_int_neg_ovf(self, gv_arg):
- gv_result = self._arg_op(gv_arg, _PPC.nego)
- gv_ov = self._ov()
- return (gv_result, gv_ov)
-
- def op_int_abs(self, gv_arg):
- gv_sign = self._arg_uimm_op(gv_arg, self.rgenop.genconst(31), _PPC.srawi)
- gv_maybe_inverted = self._arg_arg_op(gv_arg, gv_sign, _PPC.xor)
- return self._arg_arg_op(gv_sign, gv_maybe_inverted, _PPC.subf)
-
- def raisingop_int_abs_ovf(self, gv_arg):
- gv_sign = self._arg_uimm_op(gv_arg, self.rgenop.genconst(31), _PPC.srawi)
- gv_maybe_inverted = self._arg_arg_op(gv_arg, gv_sign, _PPC.xor)
- gv_result = self._arg_arg_op(gv_sign, gv_maybe_inverted, _PPC.subfo)
- return (gv_result, self._ov())
-
- def op_int_invert(self, gv_arg):
- return self._arg_op(gv_arg, _PPC.not_)
-
- def op_int_add(self, gv_x, gv_y):
- return self._arg_arg_op_with_simm(gv_x, gv_y, _PPC.add, _PPC.addi,
- commutative=True)
-
- def raisingop_int_add_ovf(self, gv_x, gv_y):
- gv_result = self._arg_arg_op(gv_x, gv_y, _PPC.addo)
- gv_ov = self._ov()
- return (gv_result, gv_ov)
-
- def op_int_sub(self, gv_x, gv_y):
- return self._arg_arg_op_with_simm(gv_x, gv_y, _PPC.sub, _PPC.subi)
-
- def raisingop_int_sub_ovf(self, gv_x, gv_y):
- gv_result = self._arg_arg_op(gv_x, gv_y, _PPC.subo)
- gv_ov = self._ov()
- return (gv_result, gv_ov)
-
- def op_int_mul(self, gv_x, gv_y):
- return self._arg_arg_op_with_simm(gv_x, gv_y, _PPC.mullw, _PPC.mulli,
- commutative=True)
-
- def raisingop_int_mul_ovf(self, gv_x, gv_y):
- gv_result = self._arg_arg_op(gv_x, gv_y, _PPC.mullwo)
- gv_ov = self._ov()
- return (gv_result, gv_ov)
-
- def op_int_floordiv(self, gv_x, gv_y):
- return self._arg_arg_op(gv_x, gv_y, _PPC.divw)
-
- ## def op_int_floordiv_zer(self, gv_x, gv_y):
-
- def op_int_mod(self, gv_x, gv_y):
- gv_dividend = self.op_int_floordiv(gv_x, gv_y)
- gv_z = self.op_int_mul(gv_dividend, gv_y)
- return self.op_int_sub(gv_x, gv_z)
-
- ## def op_int_mod_zer(self, gv_x, gv_y):
-
- def op_int_lt(self, gv_x, gv_y):
- return self._compare('lt', gv_x, gv_y)
-
- def op_int_le(self, gv_x, gv_y):
- return self._compare('le', gv_x, gv_y)
-
- def op_int_eq(self, gv_x, gv_y):
- return self._compare('eq', gv_x, gv_y)
-
- def op_int_ne(self, gv_x, gv_y):
- return self._compare('ne', gv_x, gv_y)
-
- def op_int_gt(self, gv_x, gv_y):
- return self._compare('gt', gv_x, gv_y)
-
- def op_int_ge(self, gv_x, gv_y):
- return self._compare('ge', gv_x, gv_y)
-
- op_char_lt = op_int_lt
- op_char_le = op_int_le
- op_char_eq = op_int_eq
- op_char_ne = op_int_ne
- op_char_gt = op_int_gt
- op_char_ge = op_int_ge
-
- op_unichar_eq = op_int_eq
- op_unichar_ne = op_int_ne
-
- def op_int_and(self, gv_x, gv_y):
- return self._arg_arg_op(gv_x, gv_y, _PPC.and_)
-
- def op_int_or(self, gv_x, gv_y):
- return self._arg_arg_op_with_uimm(gv_x, gv_y, _PPC.or_, _PPC.ori,
- commutative=True)
-
- def op_int_lshift(self, gv_x, gv_y):
- if gv_y.fits_in_simm():
- if abs(gv_y.value) >= 32:
- return self.rgenop.genconst(0)
- else:
- return self._arg_uimm_op(gv_x, gv_y, _PPC.slwi)
- # computing x << y when you don't know y is <=32
- # (we can assume y >= 0 though)
- # here's the plan:
- #
- # z = nltu(y, 32) (as per cwg)
- # w = x << y
- # r = w&z
- gv_a = self._arg_simm_op(gv_y, self.rgenop.genconst(32), _PPC.subfic)
- gv_b = self._arg_op(gv_y, _PPC.addze)
- gv_z = self._arg_arg_op(gv_b, gv_y, _PPC.subf)
- gv_w = self._arg_arg_op(gv_x, gv_y, _PPC.slw)
- return self._arg_arg_op(gv_z, gv_w, _PPC.and_)
-
- ## def op_int_lshift_val(self, gv_x, gv_y):
-
- def op_int_rshift(self, gv_x, gv_y):
- if gv_y.fits_in_simm():
- if abs(gv_y.value) >= 32:
- gv_y = self.rgenop.genconst(31)
- return self._arg_simm_op(gv_x, gv_y, _PPC.srawi)
- # computing x >> y when you don't know y is <=32
- # (we can assume y >= 0 though)
- # here's the plan:
- #
- # ntlu_y_32 = nltu(y, 32) (as per cwg)
- # o = srawi(x, 31) & ~ntlu_y_32
- # w = (x >> y) & ntlu_y_32
- # r = w|o
- gv_a = self._arg_uimm_op(gv_y, self.rgenop.genconst(32), _PPC.subfic)
- gv_b = self._arg_op(gv_y, _PPC.addze)
- gv_ntlu_y_32 = self._arg_arg_op(gv_b, gv_y, _PPC.subf)
-
- gv_c = self._arg_uimm_op(gv_x, self.rgenop.genconst(31), _PPC.srawi)
- gv_o = self._arg_arg_op(gv_c, gv_ntlu_y_32, _PPC.andc_)
-
- gv_e = self._arg_arg_op(gv_x, gv_y, _PPC.sraw)
- gv_w = self._arg_arg_op(gv_e, gv_ntlu_y_32, _PPC.and_)
-
- return self._arg_arg_op(gv_o, gv_w, _PPC.or_)
-
- ## def op_int_rshift_val(self, gv_x, gv_y):
-
- def op_int_xor(self, gv_x, gv_y):
- return self._arg_arg_op_with_uimm(gv_x, gv_y, _PPC.xor, _PPC.xori,
- commutative=True)
-
- ## various int_*_ovfs
-
- op_uint_is_true = op_int_is_true
- op_uint_invert = op_int_invert
-
- op_uint_add = op_int_add
- op_uint_sub = op_int_sub
- op_uint_mul = op_int_mul
-
- def op_uint_floordiv(self, gv_x, gv_y):
- return self._arg_arg_op(gv_x, gv_y, _PPC.divwu)
-
- ## def op_uint_floordiv_zer(self, gv_x, gv_y):
-
- def op_uint_mod(self, gv_x, gv_y):
- gv_dividend = self.op_uint_floordiv(gv_x, gv_y)
- gv_z = self.op_uint_mul(gv_dividend, gv_y)
- return self.op_uint_sub(gv_x, gv_z)
-
- ## def op_uint_mod_zer(self, gv_x, gv_y):
-
- def op_uint_lt(self, gv_x, gv_y):
- return self._compare_u('lt', gv_x, gv_y)
-
- def op_uint_le(self, gv_x, gv_y):
- return self._compare_u('le', gv_x, gv_y)
-
- def op_uint_eq(self, gv_x, gv_y):
- return self._compare_u('eq', gv_x, gv_y)
-
- def op_uint_ne(self, gv_x, gv_y):
- return self._compare_u('ne', gv_x, gv_y)
-
- def op_uint_gt(self, gv_x, gv_y):
- return self._compare_u('gt', gv_x, gv_y)
-
- def op_uint_ge(self, gv_x, gv_y):
- return self._compare_u('ge', gv_x, gv_y)
-
- op_uint_and = op_int_and
- op_uint_or = op_int_or
-
- op_uint_lshift = op_int_lshift
-
- ## def op_uint_lshift_val(self, gv_x, gv_y):
-
- def op_uint_rshift(self, gv_x, gv_y):
- if gv_y.fits_in_simm():
- if abs(gv_y.value) >= 32:
- return self.rgenop.genconst(0)
- else:
- return self._arg_simm_op(gv_x, gv_y, _PPC.srwi)
- # computing x << y when you don't know y is <=32
- # (we can assume y >=0 though, i think)
- # here's the plan:
- #
- # z = ngeu(y, 32) (as per cwg)
- # w = x >> y
- # r = w&z
- gv_a = self._arg_simm_op(gv_y, self.rgenop.genconst(32), _PPC.subfic)
- gv_b = self._arg_op(gv_y, _PPC.addze)
- gv_z = self._arg_arg_op(gv_b, gv_y, _PPC.subf)
- gv_w = self._arg_arg_op(gv_x, gv_y, _PPC.srw)
- return self._arg_arg_op(gv_z, gv_w, _PPC.and_)
- ## def op_uint_rshift_val(self, gv_x, gv_y):
-
- op_uint_xor = op_int_xor
-
- # ... floats ...
-
- # ... llongs, ullongs ...
-
- # here we assume that booleans are always 1 or 0 and chars are
- # always zero-padded.
-
- op_cast_bool_to_int = _identity
- op_cast_bool_to_uint = _identity
- ## def op_cast_bool_to_float(self, gv_arg):
- op_cast_char_to_int = _identity
- op_cast_unichar_to_int = _identity
- op_cast_int_to_char = _identity
-
- op_cast_int_to_unichar = _identity
- op_cast_int_to_uint = _identity
- ## def op_cast_int_to_float(self, gv_arg):
- ## def op_cast_int_to_longlong(self, gv_arg):
- op_cast_uint_to_int = _identity
- ## def op_cast_uint_to_float(self, gv_arg):
- ## def op_cast_float_to_int(self, gv_arg):
- ## def op_cast_float_to_uint(self, gv_arg):
- ## def op_truncate_longlong_to_int(self, gv_arg):
-
- # many pointer operations are genop_* special cases above
-
- op_ptr_eq = op_int_eq
- op_ptr_ne = op_int_ne
-
- op_ptr_nonzero = op_int_is_true
- op_ptr_ne = op_int_ne
- op_ptr_eq = op_int_eq
-
- def op_ptr_iszero(self, gv_arg):
- return self._compare('eq', gv_arg, self.rgenop.genconst(0))
-
- op_cast_ptr_to_int = _identity
-
- # ... address operations ...
-
- at specialize.arg(0)
-def cast_int_to_whatever(T, value):
- if isinstance(T, lltype.Ptr):
- return lltype.cast_int_to_ptr(T, value)
- elif T is llmemory.Address:
- return llmemory.cast_int_to_adr(value)
- else:
- return lltype.cast_primitive(T, value)
-
- at specialize.arg(0)
-def cast_whatever_to_int(T, value):
- if isinstance(T, lltype.Ptr):
- return lltype.cast_ptr_to_int(value)
- elif T is llmemory.Address:
- return llmemory.cast_adr_to_int(value)
- else:
- return lltype.cast_primitive(lltype.Signed, value)
-
-class RPPCGenOp(AbstractRGenOp):
-
- # the set of registers we consider available for allocation
- # we can artifically restrict it for testing purposes
- freeregs = {
- insn.GP_REGISTER:insn.gprs[3:],
- insn.FP_REGISTER:insn.fprs,
- insn.CR_FIELD:insn.crfs,
- insn.CT_REGISTER:[insn.ctr]}
- DEBUG_SCRIBBLE = option.debug_scribble
- MC_SIZE = 65536
-
- def __init__(self):
- self.mcs = [] # machine code blocks where no-one is currently writing
- self.keepalive_gc_refs = []
-
- # ----------------------------------------------------------------
- # the public RGenOp interface
-
- def newgraph(self, sigtoken, name):
- numargs = sigtoken # for now
- builder = self.newbuilder()
- builder._open()
- entrypoint = builder.asm.mc.tell()
- inputargs_gv = builder._write_prologue(sigtoken)
- return builder, IntConst(entrypoint), inputargs_gv
-
- @specialize.genconst(1)
- def genconst(self, llvalue):
- T = lltype.typeOf(llvalue)
- if T is llmemory.Address:
- return AddrConst(llvalue)
- elif isinstance(T, lltype.Primitive):
- return IntConst(lltype.cast_primitive(lltype.Signed, llvalue))
- elif isinstance(T, lltype.Ptr):
- lladdr = llmemory.cast_ptr_to_adr(llvalue)
- if T.TO._gckind == 'gc':
- self.keepalive_gc_refs.append(lltype.cast_opaque_ptr(llmemory.GCREF, llvalue))
- return AddrConst(lladdr)
- else:
- assert 0, "XXX not implemented"
-
-## @staticmethod
-## @specialize.genconst(0)
-## def constPrebuiltGlobal(llvalue):
-
- @staticmethod
- def genzeroconst(kind):
- return zero_const
-
- def replay(self, label):
- return ReplayBuilder(self), [dummy_var] * len(label.args_gv)
-
- @staticmethod
- def erasedType(T):
- if T is llmemory.Address:
- return llmemory.Address
- if isinstance(T, lltype.Primitive):
- return lltype.Signed
- elif isinstance(T, lltype.Ptr):
- return llmemory.GCREF
- else:
- assert 0, "XXX not implemented"
-
- @staticmethod
- @specialize.memo()
- def fieldToken(T, name):
- FIELD = getattr(T, name)
- if isinstance(FIELD, lltype.ContainerType):
- fieldsize = 0 # not useful for getsubstruct
- else:
- fieldsize = llmemory.sizeof(FIELD)
- return (llmemory.offsetof(T, name), fieldsize)
-
- @staticmethod
- @specialize.memo()
- def allocToken(T):
- return llmemory.sizeof(T)
-
- @staticmethod
- @specialize.memo()
- def varsizeAllocToken(T):
- if isinstance(T, lltype.Array):
- return RPPCGenOp.arrayToken(T)
- else:
- # var-sized structs
- arrayfield = T._arrayfld
- ARRAYFIELD = getattr(T, arrayfield)
- arraytoken = RPPCGenOp.arrayToken(ARRAYFIELD)
- length_offset, items_offset, item_size = arraytoken
- arrayfield_offset = llmemory.offsetof(T, arrayfield)
- return (arrayfield_offset+length_offset,
- arrayfield_offset+items_offset,
- item_size)
-
- @staticmethod
- @specialize.memo()
- def arrayToken(A):
- return (llmemory.ArrayLengthOffset(A),
- llmemory.ArrayItemsOffset(A),
- llmemory.ItemOffset(A.OF))
-
- @staticmethod
- @specialize.memo()
- def kindToken(T):
- if T is lltype.Float:
- py.test.skip("not implemented: floats in the i386^WPPC back-end")
- return None # for now
-
- @staticmethod
- @specialize.memo()
- def sigToken(FUNCTYPE):
- return len(FUNCTYPE.ARGS) # for now
-
- @staticmethod
- @specialize.arg(0)
- def read_frame_var(T, base, info, index):
- """Read from the stack frame of a caller. The 'base' is the
- frame stack pointer captured by the operation generated by
- genop_get_frame_base(). The 'info' is the object returned by
- get_frame_info(); we are looking for the index-th variable
- in the list passed to get_frame_info()."""
- place = info[index]
- if isinstance(place, StackInfo):
- #print '!!!', base, place.offset
- #print '???', [peek_word_at(base + place.offset + i)
- # for i in range(-64, 65, 4)]
- assert place.offset != 0
- value = peek_word_at(base + place.offset)
- return cast_int_to_whatever(T, value)
- else:
- assert isinstance(place, GenConst)
- return place.revealconst(T)
-
- @staticmethod
- @specialize.arg(0)
- def genconst_from_frame_var(kind, base, info, index):
- place = info[index]
- if isinstance(place, StackInfo):
- #print '!!!', base, place.offset
- #print '???', [peek_word_at(base + place.offset + i)
- # for i in range(-64, 65, 4)]
- assert place.offset != 0
- value = peek_word_at(base + place.offset)
- return IntConst(value)
- else:
- assert isinstance(place, GenConst)
- return place
-
-
- @staticmethod
- @specialize.arg(0)
- def write_frame_place(T, base, place, value):
- assert place.offset != 0
- value = cast_whatever_to_int(T, value)
- poke_word_into(base + place.offset, value)
-
- @staticmethod
- @specialize.arg(0)
- def read_frame_place(T, base, place):
- value = peek_word_at(base + place.offset)
- return cast_int_to_whatever(T, value)
-
- def check_no_open_mc(self):
- pass
-
- # ----------------------------------------------------------------
- # ppc-specific interface:
-
- MachineCodeBlock = codebuf.OwningMachineCodeBlock
- ExistingCodeBlock = codebuf.ExistingCodeBlock
-
- def open_mc(self):
- if self.mcs:
- return self.mcs.pop()
- else:
- return self.MachineCodeBlock(self.MC_SIZE) # XXX supposed infinite for now
-
- def close_mc(self, mc):
-## from pypy.jit.codegen.ppc.ppcgen.asmfunc import get_ppcgen
-## print '!!!!', cast(mc._data, c_void_p).value
-## print '!!!!', mc._data.contents[0]
-## get_ppcgen().flush2(cast(mc._data, c_void_p).value,
-## mc._size*4)
- self.mcs.append(mc)
-
- def newbuilder(self):
- return Builder(self)
-
-# a switch can take 7 instructions:
-
-# load_word rSCRATCH, gv_case.value (really two instructions)
-# cmpw crf, rSWITCH, rSCRATCH
-# load_word rSCRATCH, targetaddr (again two instructions)
-# mtctr rSCRATCH
-# beqctr crf
-
-# yay RISC :/
-
-class FlexSwitch(CodeGenSwitch):
-
- # a fair part of this code could likely be shared with the i386
- # backend.
-
- def __init__(self, rgenop, mc, switch_reg, crf, var2loc, initial_spill_offset):
- self.rgenop = rgenop
- self.crf = crf
- self.switch_reg = switch_reg
- self.var2loc = var2loc
- self.initial_spill_offset = initial_spill_offset
- self.asm = RPPCAssembler()
- self.asm.mc = mc
- self.default_target_addr = 0
-
- def add_case(self, gv_case):
- targetbuilder = self.rgenop.newbuilder()
- targetbuilder._open()
- targetbuilder.initial_var2loc = self.var2loc
- targetbuilder.initial_spill_offset = self.initial_spill_offset
- target_addr = targetbuilder.asm.mc.tell()
- p = self.asm.mc.getpos()
- # that this works depends a bit on the fixed length of the
- # instruction sequences we use to jump around. if the code is
- # ever updated to use the branch-relative instructions (a good
- # idea, btw) this will need to be thought about again
- try:
- self._add_case(gv_case, target_addr)
- except codebuf.CodeBlockOverflow:
- self.asm.mc.setpos(p)
- base = self.asm.mc.tell()
- mc = self.rgenop.open_mc()
- newmc = mc.reserve(7 * 5 + 4)
- self.rgenop.close_mc(mc)
- new_addr = newmc.tell()
- self.asm.load_word(rSCRATCH, new_addr)
- self.asm.mtctr(rSCRATCH)
- self.asm.bctr()
- size = self.asm.mc.tell() - base
- flush_icache(base, size)
- self.asm.mc = newmc
- self._add_case(gv_case, target_addr)
- return targetbuilder
-
- def _add_case(self, gv_case, target_addr):
- asm = self.asm
- base = self.asm.mc.tell()
- assert isinstance(gv_case, GenConst)
- gv_case.load_now(asm, insn.gprs[0])
- asm.cmpw(self.crf.number, rSCRATCH, self.switch_reg.number)
- asm.load_word(rSCRATCH, target_addr)
- asm.mtctr(rSCRATCH)
- asm.bcctr(12, self.crf.number*4 + 2)
- if self.default_target_addr:
- self._write_default()
- size = self.asm.mc.tell() - base
- flush_icache(base, size)
-
- def add_default(self):
- targetbuilder = self.rgenop.newbuilder()
- targetbuilder._open()
- targetbuilder.initial_var2loc = self.var2loc
- targetbuilder.initial_spill_offset = self.initial_spill_offset
- base = self.asm.mc.tell()
- self.default_target_addr = targetbuilder.asm.mc.tell()
- self._write_default()
- size = self.asm.mc.tell() - base
- flush_icache(base, size)
- return targetbuilder
-
- def _write_default(self):
- pos = self.asm.mc.getpos()
- self.asm.load_word(rSCRATCH, self.default_target_addr)
- self.asm.mtctr(rSCRATCH)
- self.asm.bctr()
- self.asm.mc.setpos(pos)
-
-global_rgenop = RPPCGenOp()
-RPPCGenOp.constPrebuiltGlobal = global_rgenop.genconst
-
-def peek_word_at(addr):
- # now the Very Obscure Bit: when translated, 'addr' is an
- # address. When not, it's an integer. It just happens to
- # make the test pass, but that's probably going to change.
- if we_are_translated():
- return addr.signed[0]
- else:
- from ctypes import cast, c_void_p, c_int, POINTER
- p = cast(c_void_p(addr), POINTER(c_int))
- return p[0]
-
-def poke_word_into(addr, value):
- # now the Very Obscure Bit: when translated, 'addr' is an
- # address. When not, it's an integer. It just happens to
- # make the test pass, but that's probably going to change.
- if we_are_translated():
- addr.signed[0] = value
- else:
- from ctypes import cast, c_void_p, c_int, POINTER
- p = cast(c_void_p(addr), POINTER(c_int))
- p[0] = value
-
-zero_const = AddrConst(llmemory.NULL)
diff --git a/pypy/jit/backend/ppc/runner.py b/pypy/jit/backend/ppc/runner.py
--- a/pypy/jit/backend/ppc/runner.py
+++ b/pypy/jit/backend/ppc/runner.py
@@ -6,16 +6,16 @@
from pypy.jit.metainterp import history, compile
from pypy.jit.metainterp.history import BoxPtr
from pypy.jit.backend.x86.assembler import Assembler386
-from pypy.jit.backend.ppc.ppcgen.arch import FORCE_INDEX_OFS
+from pypy.jit.backend.ppc.arch import FORCE_INDEX_OFS
from pypy.jit.backend.x86.profagent import ProfileAgent
from pypy.jit.backend.llsupport.llmodel import AbstractLLCPU
from pypy.jit.backend.x86 import regloc
from pypy.jit.backend.x86.support import values_array
-from pypy.jit.backend.ppc.ppcgen.ppc_assembler import AssemblerPPC
-from pypy.jit.backend.ppc.ppcgen.arch import NONVOLATILES, GPR_SAVE_AREA, WORD
-from pypy.jit.backend.ppc.ppcgen.regalloc import PPCRegisterManager, PPCFrameManager
-from pypy.jit.backend.ppc.ppcgen.codebuilder import PPCBuilder
-from pypy.jit.backend.ppc.ppcgen import register as r
+from pypy.jit.backend.ppc.ppc_assembler import AssemblerPPC
+from pypy.jit.backend.ppc.arch import NONVOLATILES, GPR_SAVE_AREA, WORD
+from pypy.jit.backend.ppc.regalloc import PPCRegisterManager, PPCFrameManager
+from pypy.jit.backend.ppc.codebuilder import PPCBuilder
+from pypy.jit.backend.ppc import register as r
import sys
from pypy.tool.ansi_print import ansi_log
@@ -37,6 +37,8 @@
self.supports_floats = False
self.total_compiled_loops = 0
self.total_compiled_bridges = 0
+
+ def setup(self):
self.asm = AssemblerPPC(self)
def setup_once(self):
@@ -113,7 +115,13 @@
def get_latest_value_ref(self, index):
return self.asm.fail_boxes_ptr.getitem(index)
+
+ def get_latest_force_token(self):
+ return self.asm.fail_force_index
+ def get_on_leave_jitted_hook(self):
+ return self.asm.leave_jitted_hook
+
# walk through the given trace and generate machine code
def _walk_trace_ops(self, codebuilder, operations):
for op in operations:
diff --git a/pypy/jit/backend/ppc/ppcgen/symbol_lookup.py b/pypy/jit/backend/ppc/symbol_lookup.py
rename from pypy/jit/backend/ppc/ppcgen/symbol_lookup.py
rename to pypy/jit/backend/ppc/symbol_lookup.py
diff --git a/pypy/jit/backend/ppc/ppcgen/test/autopath.py b/pypy/jit/backend/ppc/test/autopath.py
rename from pypy/jit/backend/ppc/ppcgen/test/autopath.py
rename to pypy/jit/backend/ppc/test/autopath.py
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_call_assembler.py b/pypy/jit/backend/ppc/test/test_call_assembler.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_call_assembler.py
rename to pypy/jit/backend/ppc/test/test_call_assembler.py
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_field.py b/pypy/jit/backend/ppc/test/test_field.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_field.py
rename to pypy/jit/backend/ppc/test/test_field.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_field.py
+++ b/pypy/jit/backend/ppc/test/test_field.py
@@ -1,6 +1,6 @@
import autopath
-from pypy.jit.backend.ppc.ppcgen.field import Field
+from pypy.jit.backend.ppc.field import Field
from py.test import raises
import random
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_form.py b/pypy/jit/backend/ppc/test/test_form.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_form.py
rename to pypy/jit/backend/ppc/test/test_form.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_form.py
+++ b/pypy/jit/backend/ppc/test/test_form.py
@@ -1,11 +1,11 @@
import autopath
-from pypy.jit.backend.ppc.ppcgen.ppc_assembler import b
+from pypy.jit.backend.ppc.ppc_assembler import b
import random
import sys
-from pypy.jit.backend.ppc.ppcgen.form import Form, FormException
-from pypy.jit.backend.ppc.ppcgen.field import Field
-from pypy.jit.backend.ppc.ppcgen.assembler import Assembler
+from pypy.jit.backend.ppc.form import Form, FormException
+from pypy.jit.backend.ppc.field import Field
+from pypy.jit.backend.ppc.assembler import Assembler
# 0 31
# +-------------------------------+
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_func_builder.py b/pypy/jit/backend/ppc/test/test_func_builder.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_func_builder.py
rename to pypy/jit/backend/ppc/test/test_func_builder.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_func_builder.py
+++ b/pypy/jit/backend/ppc/test/test_func_builder.py
@@ -1,11 +1,11 @@
import py
import random, sys, os
-from pypy.jit.backend.ppc.ppcgen.ppc_assembler import MyPPCAssembler
-from pypy.jit.backend.ppc.ppcgen.symbol_lookup import lookup
-from pypy.jit.backend.ppc.ppcgen.func_builder import make_func
-from pypy.jit.backend.ppc.ppcgen import form, func_builder
-from pypy.jit.backend.ppc.ppcgen.regname import *
+from pypy.jit.backend.ppc.ppc_assembler import MyPPCAssembler
+from pypy.jit.backend.ppc.symbol_lookup import lookup
+from pypy.jit.backend.ppc.func_builder import make_func
+from pypy.jit.backend.ppc import form, func_builder
+from pypy.jit.backend.ppc.regname import *
from pypy.jit.backend.detect_cpu import autodetect_main_model
class TestFuncBuilderTest(object):
diff --git a/pypy/jit/backend/ppc/test/test_genc_ts.py b/pypy/jit/backend/ppc/test/test_genc_ts.py
deleted file mode 100644
--- a/pypy/jit/backend/ppc/test/test_genc_ts.py
+++ /dev/null
@@ -1,16 +0,0 @@
-import py
-from pypy.jit.codegen.i386.test.test_genc_ts import I386TimeshiftingTestMixin
-from pypy.jit.timeshifter.test import test_timeshift
-from pypy.jit.codegen.ppc.rgenop import RPPCGenOp
-
-class PPCTimeshiftingTestMixin(I386TimeshiftingTestMixin):
- RGenOp = RPPCGenOp
-
-class TestTimeshiftPPC(PPCTimeshiftingTestMixin,
- test_timeshift.TestLLType):
-
- # for the individual tests see
- # ====> ../../../timeshifter/test/test_timeshift.py
-
- pass
-
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_helper.py b/pypy/jit/backend/ppc/test/test_helper.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_helper.py
rename to pypy/jit/backend/ppc/test/test_helper.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_helper.py
+++ b/pypy/jit/backend/ppc/test/test_helper.py
@@ -1,4 +1,4 @@
-from pypy.jit.backend.ppc.ppcgen.helper.assembler import (encode32, decode32)
+from pypy.jit.backend.ppc.helper.assembler import (encode32, decode32)
#encode64, decode64)
def test_encode32():
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_ppc.py b/pypy/jit/backend/ppc/test/test_ppc.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_ppc.py
rename to pypy/jit/backend/ppc/test/test_ppc.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_ppc.py
+++ b/pypy/jit/backend/ppc/test/test_ppc.py
@@ -1,13 +1,12 @@
import py
import random, sys, os
-from pypy.jit.backend.ppc.ppcgen.codebuilder import BasicPPCAssembler, PPCBuilder
-from pypy.jit.backend.ppc.ppcgen.symbol_lookup import lookup
-from pypy.jit.backend.ppc.ppcgen.regname import *
-from pypy.jit.backend.ppc.ppcgen.register import *
-from pypy.jit.backend.ppc.ppcgen import form, pystructs
+from pypy.jit.backend.ppc.codebuilder import BasicPPCAssembler, PPCBuilder
+from pypy.jit.backend.ppc.regname import *
+from pypy.jit.backend.ppc.register import *
+from pypy.jit.backend.ppc import form
from pypy.jit.backend.detect_cpu import autodetect_main_model
-from pypy.jit.backend.ppc.ppcgen.arch import IS_PPC_32, IS_PPC_64, WORD
+from pypy.jit.backend.ppc.arch import IS_PPC_32, IS_PPC_64, WORD
from pypy.rpython.lltypesystem import lltype, rffi
from pypy.rpython.annlowlevel import llhelper
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_regalloc.py b/pypy/jit/backend/ppc/test/test_regalloc.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_regalloc.py
rename to pypy/jit/backend/ppc/test/test_regalloc.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_regalloc.py
+++ b/pypy/jit/backend/ppc/test/test_regalloc.py
@@ -1,10 +1,11 @@
from pypy.rlib.objectmodel import instantiate
-from pypy.jit.backend.ppc.ppcgen.locations import (imm, RegisterLocation,
- ImmLocation, StackLocation)
-from pypy.jit.backend.ppc.ppcgen.register import *
-from pypy.jit.backend.ppc.ppcgen.codebuilder import hi, lo
-from pypy.jit.backend.ppc.ppcgen.ppc_assembler import AssemblerPPC
-from pypy.jit.backend.ppc.ppcgen.arch import WORD
+from pypy.jit.backend.ppc.locations import (imm, RegisterLocation,
+ ImmLocation, StackLocation)
+from pypy.jit.backend.ppc.register import *
+from pypy.jit.backend.ppc.codebuilder import hi, lo
+from pypy.jit.backend.ppc.ppc_assembler import AssemblerPPC
+from pypy.jit.backend.ppc.arch import WORD
+from pypy.jit.backend.ppc.locations import get_spp_offset
class MockBuilder(object):
@@ -94,23 +95,31 @@
big = 2 << 28
self.asm.regalloc_mov(imm(big), stack(7))
- exp_instr = [MI("load_imm", 0, 5),
- MI("stw", r0.value, SPP.value, -(6 * WORD + WORD)),
- MI("load_imm", 0, big),
- MI("stw", r0.value, SPP.value, -(7 * WORD + WORD))]
+ exp_instr = [MI("alloc_scratch_reg"),
+ MI("load_imm", r0, 5),
+ MI("store", r0.value, SPP.value, get_spp_offset(6)),
+ MI("free_scratch_reg"),
+
+ MI("alloc_scratch_reg"),
+ MI("load_imm", r0, big),
+ MI("store", r0.value, SPP.value, get_spp_offset(7)),
+ MI("free_scratch_reg")]
assert self.asm.mc.instrs == exp_instr
def test_mem_to_reg(self):
self.asm.regalloc_mov(stack(5), reg(10))
self.asm.regalloc_mov(stack(0), reg(0))
- exp_instrs = [MI("lwz", r10.value, SPP.value, -(5 * WORD + WORD)),
- MI("lwz", r0.value, SPP.value, -(WORD))]
+ exp_instrs = [MI("load", r10.value, SPP.value, -(5 * WORD + WORD)),
+ MI("load", r0.value, SPP.value, -(WORD))]
assert self.asm.mc.instrs == exp_instrs
def test_mem_to_mem(self):
self.asm.regalloc_mov(stack(5), stack(6))
- exp_instrs = [MI("lwz", r0.value, SPP.value, -(5 * WORD + WORD)),
- MI("stw", r0.value, SPP.value, -(6 * WORD + WORD))]
+ exp_instrs = [
+ MI("alloc_scratch_reg"),
+ MI("load", r0.value, SPP.value, get_spp_offset(5)),
+ MI("store", r0.value, SPP.value, get_spp_offset(6)),
+ MI("free_scratch_reg")]
assert self.asm.mc.instrs == exp_instrs
def test_reg_to_reg(self):
@@ -123,8 +132,8 @@
def test_reg_to_mem(self):
self.asm.regalloc_mov(reg(5), stack(10))
self.asm.regalloc_mov(reg(0), stack(2))
- exp_instrs = [MI("stw", r5.value, SPP.value, -(10 * WORD + WORD)),
- MI("stw", r0.value, SPP.value, -(2 * WORD + WORD))]
+ exp_instrs = [MI("store", r5.value, SPP.value, -(10 * WORD + WORD)),
+ MI("store", r0.value, SPP.value, -(2 * WORD + WORD))]
assert self.asm.mc.instrs == exp_instrs
def reg(i):
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_register_manager.py b/pypy/jit/backend/ppc/test/test_register_manager.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_register_manager.py
rename to pypy/jit/backend/ppc/test/test_register_manager.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_register_manager.py
+++ b/pypy/jit/backend/ppc/test/test_register_manager.py
@@ -1,4 +1,4 @@
-from pypy.jit.backend.ppc.ppcgen import regalloc, register
+from pypy.jit.backend.ppc import regalloc, register
class TestPPCRegisterManager(object):
def test_allocate_scratch_register(self):
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_stackframe.py b/pypy/jit/backend/ppc/test/test_stackframe.py
rename from pypy/jit/backend/ppc/ppcgen/test/test_stackframe.py
rename to pypy/jit/backend/ppc/test/test_stackframe.py
diff --git a/pypy/jit/backend/ppc/test/test_zll_random.py b/pypy/jit/backend/ppc/test/test_zll_random.py
new file mode 100644
--- /dev/null
+++ b/pypy/jit/backend/ppc/test/test_zll_random.py
@@ -0,0 +1,12 @@
+from pypy.jit.backend.test.test_random import check_random_function, Random
+from pypy.jit.backend.test.test_ll_random import LLtypeOperationBuilder
+from pypy.jit.backend.detect_cpu import getcpuclass
+
+CPU = getcpuclass()
+
+def test_stress():
+ cpu = CPU(None, None)
+ cpu.setup_once()
+ r = Random()
+ for i in range(1000):
+ check_random_function(cpu, LLtypeOperationBuilder, r, i, 1000)
diff --git a/pypy/jit/backend/ppc/test/test_ztranslation.py b/pypy/jit/backend/ppc/test/test_ztranslation.py
new file mode 100644
--- /dev/null
+++ b/pypy/jit/backend/ppc/test/test_ztranslation.py
@@ -0,0 +1,255 @@
+import py, os, sys
+from pypy.tool.udir import udir
+from pypy.rlib.jit import JitDriver, unroll_parameters, set_param
+from pypy.rlib.jit import PARAMETERS, dont_look_inside
+from pypy.rlib.jit import promote
+from pypy.jit.metainterp.jitprof import Profiler
+from pypy.jit.backend.detect_cpu import getcpuclass
+from pypy.jit.backend.test.support import CCompiledMixin
+from pypy.jit.codewriter.policy import StopAtXPolicy
+from pypy.translator.translator import TranslationContext
+from pypy.jit.backend.ppc.arch import IS_PPC_32, IS_PPC_64
+from pypy.config.translationoption import DEFL_GC
+from pypy.rlib import rgc
+
+class TestTranslationPPC(CCompiledMixin):
+ CPUClass = getcpuclass()
+
+ def _check_cbuilder(self, cbuilder):
+ # We assume here that we have sse2. If not, the CPUClass
+ # needs to be changed to CPU386_NO_SSE2, but well.
+ assert '-msse2' in cbuilder.eci.compile_extra
+ assert '-mfpmath=sse' in cbuilder.eci.compile_extra
+
+ def test_stuff_translates(self):
+ # this is a basic test that tries to hit a number of features and their
+ # translation:
+ # - jitting of loops and bridges
+ # - virtualizables
+ # - set_param interface
+ # - profiler
+ # - full optimizer
+ # - floats neg and abs
+
+ class Frame(object):
+ _virtualizable2_ = ['i']
+
+ def __init__(self, i):
+ self.i = i
+
+ @dont_look_inside
+ def myabs(x):
+ return abs(x)
+
+ jitdriver = JitDriver(greens = [],
+ reds = ['total', 'frame', 'j'],
+ virtualizables = ['frame'])
+ def f(i, j):
+ for param, _ in unroll_parameters:
+ defl = PARAMETERS[param]
+ set_param(jitdriver, param, defl)
+ set_param(jitdriver, "threshold", 3)
+ set_param(jitdriver, "trace_eagerness", 2)
+ total = 0
+ frame = Frame(i)
+ while frame.i > 3:
+ jitdriver.can_enter_jit(frame=frame, total=total, j=j)
+ jitdriver.jit_merge_point(frame=frame, total=total, j=j)
+ total += frame.i
+ if frame.i >= 20:
+ frame.i -= 2
+ frame.i -= 1
+ j *= -0.712
+ if j + (-j): raise ValueError
+ k = myabs(j)
+ if k - abs(j): raise ValueError
+ if k - abs(-j): raise ValueError
+ return chr(total % 253)
+ #
+ from pypy.rpython.lltypesystem import lltype, rffi
+ from pypy.rlib.libffi import types, CDLL, ArgChain
+ from pypy.rlib.test.test_libffi import get_libm_name
+ libm_name = get_libm_name(sys.platform)
+ jitdriver2 = JitDriver(greens=[], reds = ['i', 'func', 'res', 'x'])
+ def libffi_stuff(i, j):
+ lib = CDLL(libm_name)
+ func = lib.getpointer('fabs', [types.double], types.double)
+ res = 0.0
+ x = float(j)
+ while i > 0:
+ jitdriver2.jit_merge_point(i=i, res=res, func=func, x=x)
+ promote(func)
+ argchain = ArgChain()
+ argchain.arg(x)
+ res = func.call(argchain, rffi.DOUBLE)
+ i -= 1
+ return res
+ #
+ def main(i, j):
+ a_char = f(i, j)
+ a_float = libffi_stuff(i, j)
+ return ord(a_char) * 10 + int(a_float)
+ expected = main(40, -49)
+ res = self.meta_interp(main, [40, -49])
+ assert res == expected
+
+ def test_direct_assembler_call_translates(self):
+ """Test CALL_ASSEMBLER and the recursion limit"""
+ from pypy.rlib.rstackovf import StackOverflow
+
+ class Thing(object):
+ def __init__(self, val):
+ self.val = val
+
+ class Frame(object):
+ _virtualizable2_ = ['thing']
+
+ driver = JitDriver(greens = ['codeno'], reds = ['i', 'frame'],
+ virtualizables = ['frame'],
+ get_printable_location = lambda codeno: str(codeno))
+ class SomewhereElse(object):
+ pass
+
+ somewhere_else = SomewhereElse()
+
+ def change(newthing):
+ somewhere_else.frame.thing = newthing
+
+ def main(codeno):
+ frame = Frame()
+ somewhere_else.frame = frame
+ frame.thing = Thing(0)
+ portal(codeno, frame)
+ return frame.thing.val
+
+ def portal(codeno, frame):
+ i = 0
+ while i < 10:
+ driver.can_enter_jit(frame=frame, codeno=codeno, i=i)
+ driver.jit_merge_point(frame=frame, codeno=codeno, i=i)
+ nextval = frame.thing.val
+ if codeno == 0:
+ subframe = Frame()
+ subframe.thing = Thing(nextval)
+ nextval = portal(1, subframe)
+ elif frame.thing.val > 40:
+ change(Thing(13))
+ nextval = 13
+ frame.thing = Thing(nextval + 1)
+ i += 1
+ return frame.thing.val
+
+ driver2 = JitDriver(greens = [], reds = ['n'])
+
+ def main2(bound):
+ try:
+ while portal2(bound) == -bound+1:
+ bound *= 2
+ except StackOverflow:
+ pass
+ return bound
+
+ def portal2(n):
+ while True:
+ driver2.jit_merge_point(n=n)
+ n -= 1
+ if n <= 0:
+ return n
+ n = portal2(n)
+ assert portal2(10) == -9
+
+ def mainall(codeno, bound):
+ return main(codeno) + main2(bound)
+
+ res = self.meta_interp(mainall, [0, 1], inline=True,
+ policy=StopAtXPolicy(change))
+ print hex(res)
+ assert res & 255 == main(0)
+ bound = res & ~255
+ assert 1024 <= bound <= 131072
+ assert bound & (bound-1) == 0 # a power of two
+
+
+class TestTranslationRemoveTypePtrPPC(CCompiledMixin):
+ CPUClass = getcpuclass()
+
+ def _get_TranslationContext(self):
+ t = TranslationContext()
+ t.config.translation.gc = DEFL_GC # 'hybrid' or 'minimark'
+ t.config.translation.gcrootfinder = 'asmgcc'
+ t.config.translation.list_comprehension_operations = True
+ t.config.translation.gcremovetypeptr = True
+ return t
+
+ def test_external_exception_handling_translates(self):
+ jitdriver = JitDriver(greens = [], reds = ['n', 'total'])
+
+ class ImDone(Exception):
+ def __init__(self, resvalue):
+ self.resvalue = resvalue
+
+ @dont_look_inside
+ def f(x, total):
+ if x <= 30:
+ raise ImDone(total * 10)
+ if x > 200:
+ return 2
+ raise ValueError
+ @dont_look_inside
+ def g(x):
+ if x > 150:
+ raise ValueError
+ return 2
+ class Base:
+ def meth(self):
+ return 2
+ class Sub(Base):
+ def meth(self):
+ return 1
+ @dont_look_inside
+ def h(x):
+ if x < 20000:
+ return Sub()
+ else:
+ return Base()
+ def myportal(i):
+ set_param(jitdriver, "threshold", 3)
+ set_param(jitdriver, "trace_eagerness", 2)
+ total = 0
+ n = i
+ while True:
+ jitdriver.can_enter_jit(n=n, total=total)
+ jitdriver.jit_merge_point(n=n, total=total)
+ try:
+ total += f(n, total)
+ except ValueError:
+ total += 1
+ try:
+ total += g(n)
+ except ValueError:
+ total -= 1
+ n -= h(n).meth() # this is to force a GUARD_CLASS
+ def main(i):
+ try:
+ myportal(i)
+ except ImDone, e:
+ return e.resvalue
+
+ # XXX custom fishing, depends on the exact env var and format
+ logfile = udir.join('test_ztranslation.log')
+ os.environ['PYPYLOG'] = 'jit-log-opt:%s' % (logfile,)
+ try:
+ res = self.meta_interp(main, [400])
+ assert res == main(400)
+ finally:
+ del os.environ['PYPYLOG']
+
+ guard_class = 0
+ for line in open(str(logfile)):
+ if 'guard_class' in line:
+ guard_class += 1
+ # if we get many more guard_classes, it means that we generate
+ # guards that always fail (the following assert's original purpose
+ # is to catch the following case: each GUARD_CLASS is misgenerated
+ # and always fails with "gcremovetypeptr")
+ assert 0 < guard_class < 10
diff --git a/pypy/jit/backend/ppc/ppcgen/util.py b/pypy/jit/backend/ppc/util.py
rename from pypy/jit/backend/ppc/ppcgen/util.py
rename to pypy/jit/backend/ppc/util.py
--- a/pypy/jit/backend/ppc/ppcgen/util.py
+++ b/pypy/jit/backend/ppc/util.py
@@ -1,5 +1,5 @@
-from pypy.jit.codegen.ppc.ppcgen.ppc_assembler import MyPPCAssembler
-from pypy.jit.codegen.ppc.ppcgen.func_builder import make_func
+from pypy.jit.codegen.ppc.ppc_assembler import MyPPCAssembler
+from pypy.jit.codegen.ppc.func_builder import make_func
from regname import *
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