[pypy-svn] pypy arm-backend-2: Remove Restrictions on data proc imm operations

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r40664:8ef1c2341a87
Date: 2011-01-12 18:05 +0100
http://bitbucket.org/pypy/pypy/changeset/8ef1c2341a87/

Log:	Remove Restrictions on data proc imm operations

diff --git a/pypy/jit/backend/arm/instructions.py b/pypy/jit/backend/arm/instructions.py
--- a/pypy/jit/backend/arm/instructions.py
+++ b/pypy/jit/backend/arm/instructions.py
@@ -74,10 +74,9 @@
 data_proc_imm = {
     'AND_ri': {'op': 0, 'result':True, 'base':True},
     'EOR_ri': {'op': 0x2, 'result':True, 'base':True},
-    'SUB_ri': {'op': 0x4, 'rn':'!0xF', 'result':True, 'base':True},
-    #'ADR_ri': {'op': 0x4, 'rncond':'0xF', 'result':True, 'base':True},
+    'SUB_ri': {'op': 0x4, 'result':True, 'base':True},
     'RSB_ri': {'op': 0x6, 'result':True, 'base':True},
-    'ADD_ri': {'op': 0x8, 'rn':'!0xF', 'result':True, 'base':True},
+    'ADD_ri': {'op': 0x8, 'result':True, 'base':True},
     'ADC_ri': {'op': 0xA, 'result':True, 'base':True},
     'SBC_ri': {'op': 0xC, 'result':True, 'base':True},
     'RSC_ri': {'op': 0xE, 'result':True, 'base':True},

diff --git a/pypy/jit/backend/arm/instruction_builder.py b/pypy/jit/backend/arm/instruction_builder.py
--- a/pypy/jit/backend/arm/instruction_builder.py
+++ b/pypy/jit/backend/arm/instruction_builder.py
@@ -2,7 +2,6 @@
 from pypy.jit.backend.arm import instructions
 # move table lookup out of generated functions
 def define_load_store_func(name, table):
-    #  XXX W and P bits are not encoded yet
     n = (0x1 << 26
         | (table['A'] & 0x1) << 25
         | (table['op1'] & 0x1F) << 20)
@@ -118,26 +117,22 @@
 def define_data_proc_imm_func(name, table):
     n = (0x1 << 25
         | (table['op'] & 0x1F) << 20)
-    rncond = ('rn' in table and table['rn'] == '!0xF')
     if table['result'] and table['base']:
         def imm_func(self, rd, rn, imm=0, cond=cond.AL, s=0):
             if imm < 0:
                 raise ValueError
-            assert not (rncond and rn == 0xF)
             self.write32(n
                 | cond << 28
                 | s << 20
                 | imm_operation(rd, rn, imm))
     elif not table['base']:
         def imm_func(self, rd, imm=0, cond=cond.AL, s=0):
-            assert not (rncond and rn == 0xF)
             self.write32(n
                 | cond << 28
                 | s << 20
                 | imm_operation(rd, 0, imm))
     else:
         def imm_func(self, rn, imm=0, cond=cond.AL, s=0):
-            assert not (rncond and rn == 0xF)
             self.write32(n
                 | cond << 28
                 | s << 20
@@ -290,7 +285,6 @@
     | (imm & 0xFFF))
 
 def reg_operation(rt, rn, rm, imm, s, shifttype):
-    # XXX encode shiftype correctly
     return ((s & 0x1) << 20
             | (rn & 0xF) << 16
             | (rt & 0xF) << 12