[pypy-commit] pypy ppc-jit-backend: factored out some distinctions of cases between PPC32 and PPC64
hager
noreply at buildbot.pypy.org
Tue Dec 20 20:30:35 CET 2011
Author: hager <sven.hager at uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r50771:17e99f1ed45a
Date: 2011-12-20 20:30 +0100
http://bitbucket.org/pypy/pypy/changeset/17e99f1ed45a/
Log: factored out some distinctions of cases between PPC32 and PPC64
diff --git a/pypy/jit/backend/ppc/ppcgen/codebuilder.py b/pypy/jit/backend/ppc/ppcgen/codebuilder.py
--- a/pypy/jit/backend/ppc/ppcgen/codebuilder.py
+++ b/pypy/jit/backend/ppc/ppcgen/codebuilder.py
@@ -1033,6 +1033,30 @@
self.free_scratch_reg()
self.bctrl()
+ def load(self, target_reg, base_reg, offset):
+ if IS_PPC_32:
+ self.lwz(target_reg, base_reg, offset)
+ else:
+ self.ld(target_reg, base_reg, offset)
+
+ def loadx(self, target_reg, base_reg, offset_reg):
+ if IS_PPC_32:
+ self.lwzx(target_reg, base_reg, offset_reg)
+ else:
+ self.ldx(target_reg, base_reg. offset_reg)
+
+ def store(self, from_reg, base_reg, offset):
+ if IS_PPC_32:
+ self.stw(from_reg, base_reg, offset)
+ else:
+ self.std(from_reg, base_reg, offset)
+
+ def storex(self, from_reg, base_reg, offset_reg):
+ if IS_PPC_32:
+ self.stwx(from_reg, base_reg, offset_reg)
+ else:
+ self.stdx(from_reg, base_reg, offset_reg)
+
def prepare_insts_blocks(self, show=False):
self.assemble(show)
insts = self.insts
diff --git a/pypy/jit/backend/ppc/ppcgen/opassembler.py b/pypy/jit/backend/ppc/ppcgen/opassembler.py
--- a/pypy/jit/backend/ppc/ppcgen/opassembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/opassembler.py
@@ -191,35 +191,28 @@
def emit_guard_true(self, op, arglocs, regalloc):
l0 = arglocs[0]
failargs = arglocs[1:]
- if IS_PPC_32:
- self.mc.cmpwi(l0.value, 0)
- else:
- self.mc.cmpdi(l0.value, 0)
+ self.mc.cmp_op(0, l0.value, 0, imm=True)
self._emit_guard(op, failargs, c.EQ)
# # ^^^^ If this condition is met,
# # then the guard fails.
def emit_guard_false(self, op, arglocs, regalloc):
- l0 = arglocs[0]
- failargs = arglocs[1:]
- if IS_PPC_32:
- self.mc.cmpwi(l0.value, 0)
- else:
- self.mc.cmpdi(l0.value, 0)
- self._emit_guard(op, failargs, c.NE)
+ l0 = arglocs[0]
+ failargs = arglocs[1:]
+ self.mc.cmp_op(0, l0.value, 0, imm=True)
+ self._emit_guard(op, failargs, c.NE)
# TODO - Evaluate whether this can be done with
# SO bit instead of OV bit => usage of CR
# instead of XER could be more efficient
def _emit_ovf_guard(self, op, arglocs, cond):
# move content of XER to GPR
- self.mc.mfspr(r.r0.value, 1)
+ self.mc.alloc_scratch_reg()
+ self.mc.mfspr(r.SCRATCH.value, 1)
# shift and mask to get comparison result
- self.mc.rlwinm(r.r0.value, r.r0.value, 1, 0, 0)
- if IS_PPC_32:
- self.mc.cmpwi(r.r0.value, 0)
- else:
- self.mc.cmpdi(r.r0.value, 0)
+ self.mc.rlwinm(r.SCRATCH.value, r.SCRATCH.value, 1, 0, 0)
+ self.mc.cmp_op(0, r.SCRATCH.value, 0, imm=True)
+ self.mc.free_scratch_reg()
self._emit_guard(op, arglocs, cond)
def emit_guard_no_overflow(self, op, arglocs, regalloc):
@@ -235,15 +228,9 @@
if l0.is_reg():
if l1.is_imm():
- if IS_PPC_32:
- self.mc.cmpwi(l0.value, l1.getint())
- else:
- self.mc.cmpdi(l0.value, l1.getint())
+ self.mc.cmp_op(0, l0.value, l1.getint(), imm=True)
else:
- if IS_PPC_32:
- self.mc.cmpw(l0.value, l1.value)
- else:
- self.mc.cmpd(l0.value, l1.value)
+ self.mc.cmp_op(0, l0.value, l1.value)
else:
assert 0, "not implemented yet"
self._emit_guard(op, failargs, c.NE)
@@ -254,17 +241,13 @@
def _cmp_guard_class(self, op, locs, regalloc):
offset = locs[2]
if offset is not None:
+ self.mc.alloc_scratch_reg()
if offset.is_imm():
- if IS_PPC_32:
- self.mc.lwz(r.r0.value, locs[0].value, offset.value)
- else:
- self.mc.ld(r.r0.value, locs[0].value, offset.value)
+ self.mc.load(r.SCRATCH.value, locs[0].value, offset.value)
else:
- if IS_PPC_32:
- self.mc.lwzx(r.r0.value, locs[0].value, offset.value)
- else:
- self.mc.ldx(r.r0.value, locs[0].value, offset.value)
- self.mc.cmp(r.r0.value, locs[1].value)
+ self.mc.loadx(r.SCRATCH.value, locs[0].value, offset.value)
+ self.mc.cmp_op(0, r.SCRATCH.value, locs[1].value)
+ self.mc.free_scratch_reg()
else:
assert 0, "not implemented yet"
self._emit_guard(op, locs[3:], c.NE)
@@ -274,10 +257,7 @@
def emit_guard_nonnull_class(self, op, arglocs, regalloc):
offset = self.cpu.vtable_offset
- if IS_PPC_32:
- self.mc.cmpwi(arglocs[0].value, 0)
- else:
- self.mc.cmpdi(arglocs[0].value, 0)
+ self.mc.cmp_op(0, arglocs[0].value, 0, imm=True)
if offset is not None:
self._emit_guard(op, arglocs[3:], c.EQ)
else:
@@ -317,12 +297,8 @@
loc = arglocs[0]
failargs = arglocs[1:]
- if IS_PPC_32:
- self.mc.lwz(loc.value, loc.value, 0)
- self.mc.cmpwi(0, loc.value, 0)
- else:
- self.mc.ld(loc.value, loc.value, 0)
- self.mc.cmpdi(0, loc.value, 0)
+ self.mc.load(loc.value, loc.value, 0)
+ self.mc.cmp_op(0, loc.value, 0, imm=True)
self._emit_guard(op, failargs, c.NE, save_exc=True)
@@ -332,30 +308,19 @@
self.mc.load_imm(loc1, pos_exception.value)
self.mc.alloc_scratch_reg()
- if IS_PPC_32:
- self.mc.lwz(r.SCRATCH.value, loc1.value, 0)
- self.mc.cmpw(0, r.SCRATCH.value, loc.value)
- else:
- self.mc.ld(r.SCRATCH.value, loc1.value, 0)
- self.mc.cmpd(0, r.SCRATCH.value, loc.value)
+ self.mc.load(r.SCRATCH.value, loc1.value, 0)
+ self.mc.cmp_op(0, r.SCRATCH.value, loc.value)
self.mc.free_scratch_reg()
self._emit_guard(op, failargs, c.NE, save_exc=True)
self.mc.load_imm(loc, pos_exc_value.value)
if resloc:
- if IS_PPC_32:
- self.mc.lwz(resloc.value, loc.value, 0)
- else:
- self.mc.ld(resloc.value, loc.value, 0)
+ self.mc.load(resloc.value, loc.value, 0)
self.mc.alloc_scratch_reg(0)
- if IS_PPC_32:
- self.mc.stw(r.SCRATCH.value, loc.value, 0)
- self.mc.stw(r.SCRATCH.value, loc1.value, 0)
- else:
- self.mc.sd(r.SCRATCH.value, loc.value, 0)
- self.mc.sd(r.SCRATCH.value, loc1.value, 0)
+ self.mc.store(r.SCRATCH.value, loc.value, 0)
+ self.mc.store(r.SCRATCH.value, loc1.value, 0)
self.mc.free_scratch_reg()
def emit_call(self, op, args, regalloc, force_index=-1):
@@ -410,12 +375,8 @@
for i, arg in enumerate(stack_args):
offset = param_offset + i * WORD
if arg is not None:
- #self.mc.load_imm(r.SCRATCH, arg.value)
self.regalloc_mov(regalloc.loc(arg), r.SCRATCH)
- if IS_PPC_32:
- self.mc.stw(r.SCRATCH.value, r.SP.value, offset)
- else:
- self.mc.std(r.SCRATCH.value, r.SP.value, offset)
+ self.mc.store(r.SCRATCH.value, r.SP.value, offset)
self.mc.free_scratch_reg()
# collect variables that need to go in registers
@@ -541,10 +502,7 @@
def emit_arraylen_gc(self, op, arglocs, regalloc):
res, base_loc, ofs = arglocs
- if IS_PPC_32:
- self.mc.lwz(res.value, base_loc.value, ofs.value)
- else:
- self.mc.ld(res.value, base_loc.value, ofs.value)
+ self.mc.load(res.value, base_loc.value, ofs.value)
def emit_setarrayitem_gc(self, op, arglocs, regalloc):
value_loc, base_loc, ofs_loc, scale, ofs, scratch_reg = arglocs
@@ -622,15 +580,9 @@
def emit_strlen(self, op, arglocs, regalloc):
l0, l1, res = arglocs
if l1.is_imm():
- if IS_PPC_32:
- self.mc.lwz(res.value, l0.value, l1.getint())
- else:
- self.mc.ld(res.value, l0.value, l1.getint())
+ self.mc.load(res.value, l0.value, l1.getint())
else:
- if IS_PPC_32:
- self.mc.lwzx(res.value, l0.value, l1.value)
- else:
- self.mc.ldx(res.value, l0.value, l1.value)
+ self.mc.loadx(res.value, l0.value, l1.value)
def emit_strgetitem(self, op, arglocs, regalloc):
res, base_loc, ofs_loc, basesize = arglocs
@@ -833,25 +785,19 @@
def set_vtable(self, box, vtable):
if self.cpu.vtable_offset is not None:
adr = rffi.cast(lltype.Signed, vtable)
- self.mc.load_imm(r.r0, adr)
- if IS_PPC_32:
- self.mc.stw(r.r0.value, r.r3.value, self.cpu.vtable_offset)
- else:
- self.mc.std(r.r0.value, r.r3.value, self.cpu.vtable_offset)
+ self.mc.alloc_scratch_reg(adr)
+ self.mc.store(r.SCRATCH.value, r.RES.value, self.cpu.vtable_offset)
+ self.mc.free_scratch_reg()
def emit_new_array(self, op, arglocs, regalloc):
self.propagate_memoryerror_if_r3_is_null()
if len(arglocs) > 0:
value_loc, base_loc, ofs_length = arglocs
- if IS_PPC_32:
- self.mc.stw(value_loc.value, base_loc.value, ofs_length.value)
- else:
- self.mc.std(value_loc.value, base_loc.value, ofs_length.value)
+ self.mc.store(value_loc.value, base_loc.value, ofs_length.value)
emit_newstr = emit_new_array
emit_newunicode = emit_new_array
-
def write_new_force_index(self):
# for shadowstack only: get a new, unused force_index number and
# write it to FORCE_INDEX_OFS. Used to record the call shape
@@ -895,10 +841,7 @@
loc_base = arglocs[0]
self.mc.alloc_scratch_reg()
- if IS_PPC_32:
- self.mc.lwz(r.SCRATCH.value, loc_base.value, 0)
- else:
- self.mc.ld(r.SCRATCH.value, loc_base.value, 0)
+ self.mc.load(r.SCRATCH.value, loc_base.value, 0)
# get the position of the bit we want to test
bitpos = descr.jit_wb_if_flag_bitpos
@@ -977,10 +920,7 @@
resloc = regalloc.try_allocate_reg(resbox)
assert resloc is r.RES
self.mc.alloc_scratch_reg(value)
- if IS_PPC_32:
- self.mc.cmpw(0, resloc.value, r.SCRATCH.value)
- else:
- self.mc.cmpd(0, resloc.value, r.SCRATCH.value)
+ self.mc.cmp_op(0, resloc.value, r.SCRATCH.value)
self.mc.free_scratch_reg()
regalloc.possibly_free_var(resbox)
@@ -1034,10 +974,7 @@
self.alloc_scratch_reg()
self.mov_loc_loc(arglocs[1], r.SCRATCH)
self.mc.li(resloc.value, 0)
- if IS_PPC_32:
- self.mc.stwx(resloc.value, 0, r.SCRATCH.value)
- else:
- self.mc.stdx(resloc.value, 0, r.SCRATCH.value)
+ self.mc.storex(resloc.value, 0, r.SCRATCH.value)
self.free_scratch_reg()
regalloc.possibly_free_var(resbox)
@@ -1058,10 +995,7 @@
if op.result.type == FLOAT:
assert 0, "not implemented yet"
else:
- if IS_PPC_32:
- self.mc.lwzx(resloc.value, 0, r.SCRATCH.value)
- else:
- self.mc.ldx(resloc.value, 0, r.SCRATCH.value)
+ self.mc.loadx(resloc.value, 0, r.SCRATCH.value)
self.mc.free_scratch_reg()
# merge point
@@ -1072,12 +1006,8 @@
pmc.overwrite()
self.mc.alloc_scratch_reg()
- if IS_PPC_32:
- self.mc.cmpwi(0, r.SCRATCH.value, 0)
- self.mc.lwz(r.SCRATCH.value, r.SPP.value, 0)
- else:
- self.mc.cmpdi(0, r.SCRATCH.value, 0)
- self.mc.ld(r.SCRATCH.value, r.SPP.value, 0)
+ self.mc.cmp_op(0, r.SCRATCH.value, 0, imm=True)
+ self.mc.load(r.SCRATCH.value, r.SPP.value, 0)
self.mc.cror(2, 1, 2)
self.mc.free_scratch_reg()
@@ -1086,12 +1016,8 @@
def emit_guard_call_may_force(self, op, guard_op, arglocs, regalloc):
ENCODING_AREA = len(r.MANAGED_REGS) * WORD
self.mc.alloc_scratch_reg()
- if IS_PPC_32:
- self.mc.lwz(r.SCRATCH.value, r.SPP.value, ENCODING_AREA)
- self.mc.cmpwi(0, r.SCRATCH.value, 0)
- else:
- self.mc.ld(r.SCRATCH.value, r.SPP.value, ENCODING_AREA)
- self.mc.cmpdi(0, r.SCRATCH.value, 0)
+ self.mc.load(r.SCRATCH.value, r.SPP.value, ENCODING_AREA)
+ self.mc.cmp_op(0, r.SCRATCH.value, 0, imm=True)
self.mc.free_scratch_reg()
self._emit_guard(guard_op, arglocs, c.LT)
diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
@@ -112,23 +112,15 @@
# save r31 later on
if reg.value == r.SPP.value:
continue
- if IS_PPC_32:
- self.mc.stw(reg.value, r.SPP.value,
- self.OFFSET_SPP_TO_GPR_SAVE_AREA + WORD * i)
- else:
- self.mc.std(reg.value, r.SPP.value,
- self.OFFSET_SPP_TO_GPR_SAVE_AREA + WORD * i)
+ self.mc.store(reg.value, r.SPP.value,
+ self.OFFSET_SPP_TO_GPR_SAVE_AREA + WORD * i)
def _restore_nonvolatiles(self, mc, spp_reg):
""" restore nonvolatile GPRs from GPR SAVE AREA
"""
for i, reg in enumerate(NONVOLATILES):
- if IS_PPC_32:
- mc.lwz(reg.value, spp_reg.value,
- self.OFFSET_SPP_TO_GPR_SAVE_AREA + WORD * i)
- else:
- mc.ld(reg.value, spp_reg.value,
- self.OFFSET_SPP_TO_GPR_SAVE_AREA + WORD * i)
+ mc.load(reg.value, spp_reg.value,
+ self.OFFSET_SPP_TO_GPR_SAVE_AREA + WORD * i)
def get_asmmemmgr_blocks(self, looptoken):
clt = looptoken.compiled_loop_token
@@ -151,13 +143,12 @@
self.mc.mflr(r.SCRATCH.value) # move old link register
# save old link register in previous frame
self.mc.stw(r.SCRATCH.value, r.SP.value, frame_depth + WORD)
- # save r31 at the bottom of the stack frame
- self.mc.stw(r.SPP.value, r.SP.value, WORD)
else:
self.mc.stdu(r.SP.value, r.SP.value, -frame_depth)
self.mc.mflr(r.SCRATCH.value)
self.mc.std(r.SCRATCH.value, r.SP.value, frame_depth + 2 * WORD)
- self.mc.std(r.SPP.value, r.SP.value, WORD)
+ # save SPP at the bottom of the stack frame
+ self.mc.store(r.SPP.value, r.SP.value, WORD)
# compute spilling pointer (SPP)
self.mc.addi(r.SPP.value, r.SP.value,
@@ -168,12 +159,8 @@
assert NONVOLATILES[-1] == r.SPP
ofs_to_r31 = (self.OFFSET_SPP_TO_GPR_SAVE_AREA +
WORD * (len(NONVOLATILES)-1))
- if IS_PPC_32:
- self.mc.lwz(r.r30.value, r.SP.value, WORD)
- self.mc.stw(r.r30.value, r.SPP.value, ofs_to_r31)
- else:
- self.mc.ld(r.r30.value, r.SP.value, WORD)
- self.mc.std(r.r30.value, r.SPP.value, ofs_to_r31)
+ self.mc.load(r.r30.value, r.SP.value, WORD)
+ self.mc.store(r.r30.value, r.SPP.value, ofs_to_r31)
def setup_failure_recovery(self):
@@ -336,10 +323,7 @@
r11_value = descr[2]
# load parameters into parameter registers
- if IS_PPC_32:
- mc.lwz(r.r3.value, r.SPP.value, self.ENCODING_AREA) # address of state encoding
- else:
- mc.ld(r.r3.value, r.SPP.value, self.ENCODING_AREA)
+ mc.load(r.r3.value, r.SPP.value, self.ENCODING_AREA) # address of state encoding
mc.mr(r.r4.value, r.SPP.value) # load spilling pointer
#
# load address of decoding function into SCRATCH
@@ -361,10 +345,7 @@
mc.mr(r.r5.value, r.SPP.value)
self._restore_nonvolatiles(mc, r.r5)
# load old backchain into r4
- if IS_PPC_32:
- mc.lwz(r.r4.value, r.r5.value, self.OFFSET_SPP_TO_OLD_BACKCHAIN + WORD)
- else:
- mc.ld(r.r4.value, r.r5.value, self.OFFSET_SPP_TO_OLD_BACKCHAIN + 2 * WORD)
+ mc.load(r.r4.value, r.r5.value, self.OFFSET_SPP_TO_OLD_BACKCHAIN + WORD)
mc.mtlr(r.r4.value) # restore LR
# From SPP, we have a constant offset to the old backchain. We use the
# SPP to re-establish the old backchain because this exit stub is
@@ -380,10 +361,7 @@
"""
for i in range(len(r.MANAGED_REGS)):
reg = r.MANAGED_REGS[i]
- if IS_PPC_32:
- mc.stw(reg.value, r.SPP.value, i * WORD)
- else:
- mc.std(reg.value, r.SPP.value, i * WORD)
+ mc.store(reg.value, r.SPP.value, i * WORD)
# Load parameters from fail args into locations (stack or registers)
def gen_bootstrap_code(self, nonfloatlocs, inputargs):
@@ -453,10 +431,7 @@
else:
loc = nonfloatlocs[i]
if loc.is_reg():
- if IS_PPC_32:
- self.mc.lwz(loc.value, r.SPP.value, stack_position)
- else:
- self.mc.ld(loc.value, r.SPP.value, stack_position)
+ self.mc.load(loc.value, r.SPP.value, stack_position)
count += 1
elif loc.is_vfp_reg():
assert 0, "not implemented yet"
@@ -466,10 +441,7 @@
elif loc.type == INT or loc.type == REF:
count += 1
self.mc.alloc_scratch_reg()
- if IS_PPC_32:
- self.mc.lwz(r.SCRATCH.value, r.SPP.value, stack_position)
- else:
- self.mc.ld(r.SCRATCH.value, r.SPP.value, stack_position)
+ self.mc.load(r.SCRATCH.value, r.SPP.value, stack_position)
self.mov_loc_loc(r.SCRATCH, loc)
self.mc.free_scratch_reg()
else:
@@ -777,10 +749,7 @@
# store addr in force index field
self.mc.alloc_scratch_reg(memaddr)
- if IS_PPC_32:
- self.mc.stw(r.SCRATCH.value, r.SPP.value, self.ENCODING_AREA)
- else:
- self.mc.std(r.SCRATCH.value, r.SPP.value, self.ENCODING_AREA)
+ self.mc.store(r.SCRATCH.value, r.SPP.value, self.ENCODING_AREA)
self.mc.free_scratch_reg()
if save_exc:
@@ -834,10 +803,7 @@
self.mc.alloc_scratch_reg()
offset = loc.as_key() * WORD - WORD
self.mc.load_imm(r.SCRATCH.value, value)
- if IS_PPC_32:
- self.mc.stw(r.SCRATCH.value, r.SPP.value, offset)
- else:
- self.mc.std(r.SCRATCH.value, r.SPP.value, offset)
+ self.mc.store(r.SCRATCH.value, r.SPP.value, offset)
self.mc.free_scratch_reg()
return
assert 0, "not supported location"
@@ -846,21 +812,14 @@
# move from memory to register
if loc.is_reg():
reg = loc.as_key()
- if IS_PPC_32:
- self.mc.lwz(reg, r.SPP.value, offset)
- else:
- self.mc.ld(reg, r.SPP.value, offset)
+ self.mc.load(reg, r.SPP.value, offset)
return
# move in memory
elif loc.is_stack():
target_offset = loc.as_key() * WORD - WORD
self.mc.alloc_scratch_reg()
- if IS_PPC_32:
- self.mc.lwz(r.SCRATCH.value, r.SPP.value, offset)
- self.mc.stw(r.SCRATCH.value, r.SPP.value, target_offset)
- else:
- self.mc.ld(r.SCRATCH.value, r.SPP.value, offset)
- self.mc.std(r.SCRATCH.value, r.SPP.value, target_offset)
+ self.mc.load(r.SCRATCH.value, r.SPP.value, offset)
+ self.mc.store(r.SCRATCH.value, r.SPP.value, target_offset)
self.mc.free_scratch_reg()
return
assert 0, "not supported location"
@@ -874,10 +833,7 @@
# move to memory
elif loc.is_stack():
offset = loc.as_key() * WORD - WORD
- if IS_PPC_32:
- self.mc.stw(reg, r.SPP.value, offset)
- else:
- self.mc.std(reg, r.SPP.value, offset)
+ self.mc.store(reg, r.SPP.value, offset)
return
assert 0, "not supported location"
assert 0, "not supported location"
@@ -987,11 +943,10 @@
return 0
def _write_fail_index(self, fail_index):
+ self.mc.alloc_scratch_reg(fail_index)
self.mc.load_imm(r.SCRATCH, fail_index)
- if IS_PPC_32:
- self.mc.stw(r.SCRATCH.value, r.SPP.value, self.ENCODING_AREA)
- else:
- self.mc.std(r.SCRATCH.value, r.SPP.value, self.ENCODING_AREA)
+ self.mc.store(r.SCRATCH.value, r.SPP.value, self.ENCODING_AREA)
+ self.mc.free_scratch_reg()
def load(self, loc, value):
assert loc.is_reg() and value.is_imm()
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