[pypy-svn] r78199 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

[david at codespeak.net]

Author: david
Date: Fri Oct 22 13:59:44 2010
New Revision: 78199

Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Add instr. to call coprocessor

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py	Fri Oct 22 13:59:44 2010
@@ -1,6 +1,6 @@
 from pypy.jit.backend.arm import conditions as cond
 from pypy.jit.backend.arm import instructions
-
+# move table lookup out of generated functions
 def define_load_store_func(name, table):
     #  XXX W and P bits are not encoded yet
     n = (0x1 << 26
@@ -92,6 +92,19 @@
                         | reg_operation(rd, rn, rm, imm, s, shifttype))
     return f
 
+def define_supervisor_and_coproc(name, table):
+    n = (0x3 << 26 | (table['op1'] & 0x3F) << 20 | (table['op'] & 0x1) << 4)
+    def f(self, coproc, opc1, rt, crn, crm, opc2=0, cond=cond.AL):
+        self.write32(n
+                    | cond << 28
+                    | (opc1 & 0x7) << 21
+                    | (crn & 0xF) << 16
+                    | (rt & 0xF) << 12
+                    | (coproc & 0xF) << 8
+                    | (opc2 & 0x7) << 5
+                    | (crm & 0xF))
+    return f
+
 def imm_operation(rt, rn, imm):
     return ((rn & 0xFF) << 16
     | (rt & 0xFF) << 12
@@ -119,3 +132,6 @@
 
     for key, val in instructions.data_proc_imm.iteritems():
         define_instruction(define_data_proc_imm, key, val, target)
+
+    for key, val in instructions.supervisor_and_coproc.iteritems():
+        define_instruction(define_supervisor_and_coproc, key, val, target)

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py	Fri Oct 22 13:59:44 2010
@@ -52,3 +52,7 @@
     'BIC_ri': {'op': 0x1C, 'rncond':'', 'result':True, 'base':True},
     'MVN_ri': {'op': 0x1E, 'rncond':'', 'result':True, 'base':False},
 }
+
+supervisor_and_coproc = {
+    'MCR': {'op1': 0x20, 'op': 1, 'rn':0, 'coproc':0},
+}

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	Fri Oct 22 13:59:44 2010
@@ -114,6 +114,11 @@
         self.cb.CMP(r.r3, 123)
         self.assert_equal('CMP r3, #123')
 
+    def test_mcr(self):
+        self.cb.MCR(15, 0, r.r1, 7, 10,0)
+
+        self.assert_equal('MCR P15, 0, r1, c7, c10, 0')
+
 
 class TestInstrCodeBuilderForGeneratedInstr(ASMTest):
     def setup_method(self, ffuu_method):