[pypy-svn] r77972 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test
david at codespeak.net
david at codespeak.net
Fri Oct 15 11:51:26 CEST 2010
Author: david
Date: Fri Oct 15 11:51:24 2010
New Revision: 77972
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Encode ARM imm data instructions
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py Fri Oct 15 11:51:24 2010
@@ -10,33 +10,6 @@
self._data = alloc(1024)
self._pos = 0
- def ADD_ri(self, rt, rn, imm, cond=cond.AL):
- # XXX S bit
- self.write32(cond << 28
- | 2 << 24
- | 8 << 20
- | (rn & 0xF) << 16
- | (rt & 0xF) << 12
- | (imm & 0xFFF))
-
- def SUB_ri(self, rd, rn, imm=0, cond=cond.AL, s=0):
- self.write32(cond << 28
- | 9 << 22
- | (s & 0x1) << 20
- | (rn & 0xF) << 16
- | (rd & 0xF) << 12
- | (imm & 0xFFF))
-
- def MOV_ri(self, rt, imm=0, cond=cond.AL):
- # XXX Check the actual allowed size for imm
- # XXX S bit
- self.write32(cond << 28
- | 0x3 << 24
- | 0xA << 20
- #| 0x0 << 16
- | (rt & 0xF) << 12
- | (imm & 0xFFF))
-
def PUSH(self, regs, cond=cond.AL):
assert reg.sp not in regs
instr = self._encode_reg_list(cond << 28 | 0x92D << 16, regs)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py Fri Oct 15 11:51:24 2010
@@ -17,9 +17,7 @@
| (p & 0x1) << 24
| (u & 0x1) << 23
| (w & 0x1) << 21
- | (rn & 0xFF) << 16
- | (rt & 0xFF) << 12
- | (imm & 0xFFF))
+ | imm_operation(rt, rn, imm))
else:
def f(self, rt, rn, rm, imm=0, cond=cond.AL, s=0, shifttype=0):
p = 1
@@ -32,6 +30,31 @@
| (w & 0x1) << 21
| reg_operation(rt, rn, rm, imm, s, shifttype))
return f
+def define_data_proc_imm(name, table):
+ n = (0x1 << 25
+ | (table['op'] & 0x1F) << 20)
+ if table['result'] and table['base']:
+ def imm_func(self, rd, rn, imm=0, cond=cond.AL, s=0):
+ # XXX check condition on rn
+ self.write32(n
+ | cond << 28
+ | s << 20
+ | imm_operation(rd, rn, imm))
+ elif not table['base']:
+ def imm_func(self, rd, imm=0, cond=cond.AL, s=0):
+ # XXX check condition on rn
+ self.write32(n
+ | cond << 28
+ | s << 20
+ | imm_operation(rd, 0, imm))
+ else:
+ def imm_func(self, rn, imm=0, cond=cond.AL, s=0):
+ # XXX check condition on rn
+ self.write32(n
+ | cond << 28
+ | s << 20
+ | imm_operation(0, rn, imm))
+ return imm_func
def define_data_proc(name, table):
n = ((table['op1'] & 0x1F) << 20
@@ -69,6 +92,10 @@
| reg_operation(rd, rn, rm, imm, s, shifttype))
return f
+def imm_operation(rt, rn, imm):
+ return ((rn & 0xFF) << 16
+ | (rt & 0xFF) << 12
+ | (imm & 0xFFF))
def reg_operation(rt, rn, rm, imm, s, shifttype):
# XXX encode shiftype correctly
@@ -79,11 +106,16 @@
| (shifttype & 0x3) << 5
| (rm & 0xFF))
+def define_instruction(builder, key, val, target):
+ f = builder(key, val)
+ setattr(target, key, f)
+
def define_instructions(target):
for key, val in instructions.load_store.iteritems():
- f = define_load_store_func(key, val)
- setattr(target, key, f)
+ define_instruction(define_load_store_func, key, val, target)
for key, val in instructions.data_proc.iteritems():
- f = define_data_proc(key, val)
- setattr(target, key, f)
+ define_instruction(define_data_proc, key, val, target)
+
+ for key, val in instructions.data_proc_imm.iteritems():
+ define_instruction(define_data_proc_imm, key, val, target)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py Fri Oct 15 11:51:24 2010
@@ -32,3 +32,23 @@
#'RRX_ri': {'op1':0x1A, 'op2':0, 'op3':0x3, 'op2cond':'0', 'result':False, 'base':True},
'ROR_ri': {'op1':0x1A, 'op2':0x0, 'op3':0x3, 'op2cond':'!0', 'result':True, 'base':False},
}
+
+data_proc_imm = {
+ 'ADD_ri': {'op': 0, 'rncond':'', 'result':True, 'base':True},
+ 'EOR_ri': {'op': 0x2, 'rncond':'', 'result':True, 'base':True},
+ 'SUB_ri': {'op': 0x4, 'rncond':'!0xF', 'result':True, 'base':True},
+ #'ADR_ri': {'op': 0x4, 'rncond':'0xF', 'result':True, 'base':True},
+ 'RSB_ri': {'op': 0x6, 'rncond':'', 'result':True, 'base':True},
+ 'ADD_ri': {'op': 0x8, 'rncond':'!0xF', 'result':True, 'base':True},
+ 'ADC_ri': {'op': 0xA, 'rncond':'', 'result':True, 'base':True},
+ 'SBC_ri': {'op': 0xC, 'rncond':'', 'result':True, 'base':True},
+ 'RSC_ri': {'op': 0xE, 'rncond':'', 'result':True, 'base':True},
+ 'TST_ri': {'op': 0x11, 'rncond':'', 'result':False, 'base':True},
+ 'TEQ_ri': {'op': 0x13, 'rncond':'', 'result':False, 'base':True},
+ 'CMP_ri': {'op': 0x15, 'rncond':'', 'result':False, 'base':True},
+ 'CMN_ri': {'op': 0x17, 'rncond':'', 'result':False, 'base':True},
+ 'ORR_ri': {'op': 0x18, 'rncond':'', 'result':True, 'base':True},
+ 'MOV_ri': {'op': 0x1A, 'rncond':'', 'result':True, 'base':False},
+ 'BIC_ri': {'op': 0x1C, 'rncond':'', 'result':True, 'base':True},
+ 'MVN_ri': {'op': 0x1E, 'rncond':'', 'result':True, 'base':False},
+}
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py Fri Oct 15 11:51:24 2010
@@ -120,17 +120,43 @@
self.cb = CodeBuilder()
def build_tests():
+ test_name = 'test_generated_%s'
for key, value in instructions.load_store.iteritems():
if value['imm']:
f = gen_test_imm_func
else:
f = gen_test_reg_func
- test = f(key, value)
- setattr(TestInstrCodeBuilderForGeneratedInstr, 'test_%s' % key, test)
+ build_test(f, key, value, test_name)
for key, value, in instructions.data_proc.iteritems():
- test = gen_test_data_reg_func(key, value)
- setattr(TestInstrCodeBuilderForGeneratedInstr, 'test_%s' % key, test)
+ build_test(gen_test_data_reg_func, key, value, test_name)
+
+ for key, value, in instructions.data_proc_imm.iteritems():
+ build_test(gen_test_data_proc_imm_func, key, value, test_name)
+
+# XXX refactor this functions
+
+def build_test(builder, key, value, test_name):
+ test = builder(key, value)
+ setattr(TestInstrCodeBuilderForGeneratedInstr, test_name % key, test)
+
+def gen_test_data_proc_imm_func(name, table):
+ if table['result'] and table['base']:
+ def f(self):
+ func = getattr(self.cb, name)
+ func(r.r3, r.r7, 23)
+ self.assert_equal('%s r3, r7, #23' % name[:name.index('_')])
+ elif not table['base']:
+ def f(self):
+ func = getattr(self.cb, name)
+ func(r.r3, 23)
+ self.assert_equal('%s r3, #23' % name[:name.index('_')])
+ else:
+ def f(self):
+ func = getattr(self.cb, name)
+ func(r.r3, 23)
+ self.assert_equal('%s r3, #23' % name[:name.index('_')])
+ return f
def gen_test_imm_func(name, table):
def f(self):
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