[pypy-svn] r79435 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test
david at codespeak.net
david at codespeak.net
Tue Nov 23 20:57:27 CET 2010
Author: david
Date: Tue Nov 23 20:57:25 2010
New Revision: 79435
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py
Log:
Fix a register allocation issue in emit_guard_int_mul_ovf
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Tue Nov 23 20:57:25 2010
@@ -89,7 +89,7 @@
def emit_op_int_mul(self, op, regalloc, fcond):
a0 = op.getarg(0)
a1 = op.getarg(1)
- reg1 = regalloc.make_sure_var_in_reg(a0, imm_fine=False)
+ reg1 = regalloc.make_sure_var_in_reg(a0, [a1], imm_fine=False)
reg2 = regalloc.make_sure_var_in_reg(a1, [a0], imm_fine=False)
res = regalloc.force_allocate_reg(op.result, [a0, a1])
self.mc.MUL(res.value, reg1.value, reg2.value)
@@ -98,11 +98,10 @@
return fcond
#ref: http://blogs.arm.com/software-enablement/detecting-overflow-from-mul/
- f = False
def emit_guard_int_mul_ovf(self, op, guard, regalloc, fcond):
a0 = op.getarg(0)
a1 = op.getarg(1)
- reg1 = regalloc.make_sure_var_in_reg(a0, imm_fine=False)
+ reg1 = regalloc.make_sure_var_in_reg(a0, [a1], imm_fine=False)
reg2 = regalloc.make_sure_var_in_reg(a1, [a0], imm_fine=False)
res = regalloc.force_allocate_reg(op.result, [a0, a1])
self.mc.SMULL(res.value, r.ip.value, reg1.value, reg2.value, cond=fcond)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py Tue Nov 23 20:57:25 2010
@@ -28,7 +28,6 @@
cpu = self.cpu
inp = [BoxInt(i) for i in range(1, 15)]
out = [BoxInt(i) for i in range(1, 15)]
- #out.reverse()
looptoken = LoopToken()
operations = [
ResOperation(rop.INT_ADD, [inp[0] , inp[1]], out[0]),
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