[pypy-svn] r74751 - in pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86: . test

[jcreigh at codespeak.net]

Author: jcreigh
Date: Tue May 25 21:35:16 2010
New Revision: 74751

Modified:
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
Log:
add a few more float operations

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py	Tue May 25 21:35:16 2010
@@ -698,16 +698,16 @@
 
     def genop_float_neg(self, op, arglocs, resloc):
         # Following what gcc does: res = x ^ 0x8000000000000000
-        self.mc.XORPD(arglocs[0], self.loc_float_const_neg)
+        self.mc.XORPD_rj(arglocs[0].value, self.loc_float_const_neg)
 
     def genop_float_abs(self, op, arglocs, resloc):
         # Following what gcc does: res = x & 0x7FFFFFFFFFFFFFFF
-        self.mc.ANDPD(arglocs[0], self.loc_float_const_abs)
+        self.mc.ANDPD_rj(arglocs[0].value, self.loc_float_const_abs)
 
     def genop_guard_float_is_true(self, op, guard_op, addr, arglocs, resloc):
         guard_opnum = guard_op.opnum
         loc0, loc1 = arglocs
-        self.mc.XORPD(loc0, loc0)
+        self.mc.XORPD_rr(loc0.value, loc0.value)
         self.mc.UCOMISD(loc0, loc1)
         mc = self.mc._mc
         if guard_opnum == rop.GUARD_TRUE:
@@ -720,7 +720,7 @@
             return self.implement_guard(addr)
 
     def genop_float_is_true(self, op, arglocs, resloc):
-        self.mc.XORPD(arglocs[0], arglocs[0])
+        self.mc.XORPD_rr(arglocs[0].value, arglocs[0].value)
         self.genop_float_ne(op, arglocs, resloc)
 
     def genop_cast_float_to_int(self, op, arglocs, resloc):

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py	Tue May 25 21:35:16 2010
@@ -161,6 +161,7 @@
     MULSD = _binaryop('MULSD')
     DIVSD = _binaryop('DIVSD')
     UCOMISD = _binaryop('UCOMISD')
+    CVTSI2SD = _binaryop('CVTSI2SD')
 
 
     def CALL(self, loc):

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py	Tue May 25 21:35:16 2010
@@ -548,6 +548,17 @@
     UCOMISD_rb = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), stack_bp(2))
     UCOMISD_rj = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), '\x05', immediate(2))
 
+    # Conversion
+    # FIXME: Super confusing! The source is a GPR/mem, the destination is an xmm register
+    CVTSI2SD_rr = xmminsn('\xF2', rex_nw, '\x0F\x2A', register(1, 8), register(2), '\xC0')
+    CVTSI2SD_rb = xmminsn('\xF2', rex_nw, '\x0F\x2A', register(1, 8), stack_bp(2))
+
+    # Bitwise
+    ANDPD_rj = xmminsn('\x66', rex_nw, '\x0F\x54', register(1, 8), '\x05', immediate(2))
+
+    XORPD_rr = xmminsn('\x66', rex_nw, '\x0F\x57', register(1, 8), register(2), '\xC0')
+    XORPD_rj = xmminsn('\x66', rex_nw, '\x0F\x57', register(1, 8), '\x05', immediate(2))
+
     # ------------------------------------------------------------
 
 Conditions = {
@@ -634,6 +645,10 @@
         py.test.skip("DIVSD_rj unsupported")
     def UCOMISD_rj(self, xmm_reg, mem_immed):
         py.test.skip("UCOMISD_rj unsupported")
+    def ANDPD_rj(self, xmm_reg, mem_immed):
+        py.test.skip("ANDPD_rj unsupported")
+    def XORPD_rj(self, xmm_reg, mem_immed):
+        py.test.skip("XORPD_rj unsupported")
 
 
 # ____________________________________________________________

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py	Tue May 25 21:35:16 2010
@@ -225,6 +225,11 @@
             if methname.startswith('SHL') or methname.startswith('SAR') or methname.startswith('SHR'):
                 # XXX: Would be nice to test these automatically
                 py.test.skip('Shifts must be tested manually')
+            if methname.startswith('CVT'):
+                # Can't test automatically right now, we don't know
+                # which register types to use
+                py.test.skip('Skipping CVT instructions for now')
+
             return [args]
 
     def get_code_checker_class(self):