[pypy-svn] r62908 - in pypy/branch/pyjitpl5/pypy/jit/backend/x86: . test

[fijal at codespeak.net]

Author: fijal
Date: Thu Mar 12 21:38:31 2009
New Revision: 62908

Modified:
   pypy/branch/pyjitpl5/pypy/jit/backend/x86/regalloc.py
   pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_regalloc.py
Log:
a partial fix. test segfault so far


Modified: pypy/branch/pyjitpl5/pypy/jit/backend/x86/regalloc.py
==============================================================================
--- pypy/branch/pyjitpl5/pypy/jit/backend/x86/regalloc.py	(original)
+++ pypy/branch/pyjitpl5/pypy/jit/backend/x86/regalloc.py	Thu Mar 12 21:38:31 2009
@@ -950,6 +950,8 @@
         ops = []
         laterops = []
         middle_ops = []
+        reloaded = []
+        middle_busy_regs = []
         for i in range(len(op.args)):
             arg = op.args[i]
             mp = op.jump_target
@@ -961,7 +963,7 @@
                     if not isinstance(res, REG):
                         ops.append(Store(arg, self.loc(arg), self.stack_bindings[arg]))
                     elif res is self.reg_bindings[arg]:
-                        pass
+                        middle_busy_regs.append(res)
                     else:
                         # register, but wrong
                         # we're going to need it (otherwise it'll be dead), so
@@ -985,10 +987,32 @@
                         if isinstance(res, REG):
                             laterops.append(Load(arg, self.loc(arg), res))
                         else:
-                            if not we_are_translated():
-                                assert repr(res) == repr(self.loc(arg))
+                            if self.loc(arg).position != res.position:
+                                reloaded.append((arg, self.loc(arg), res))
             elif isinstance(arg, Const):
                 laterops.append(Load(arg, self.loc(arg), res))
+        if reloaded:
+            self.eventually_free_vars(op.args)
+            middleops = []
+            # XXX performance
+            free_reg = None
+            last_middle_op = None
+            for reg in REGS:
+                if reg not in middle_busy_regs:
+                    free_reg = reg
+                    break
+            if free_reg is None:
+                # a very rare case
+                v = self.reg_bindings.keys()[0]
+                free_reg = self.reg_bindings[v]
+                ops.append(Store(v, self.loc(v), self.stack_loc(v)))
+                last_middle_op = Load(v, self.stack_loc(v), self.loc(v))
+            for v, from_l, to_l in reloaded:
+                middleops.append(Load(v, from_l, free_reg))
+                middleops.append(Store(v, free_reg, to_l))
+            if last_middle_op is not None:
+                middleops.append(last_middle_op)
+            return ops + middleops + laterops + [PerformDiscard(op, [])]
         self.eventually_free_vars(op.args)
         return ops + laterops + [PerformDiscard(op, [])]
 

Modified: pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_regalloc.py
==============================================================================
--- pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_regalloc.py	(original)
+++ pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_regalloc.py	Thu Mar 12 21:38:31 2009
@@ -183,6 +183,8 @@
     cpu = CPU(rtyper=None, stats=FakeStats())
     cpu.set_meta_interp(meta_interp)
     TP = lltype.GcStruct('x', ('y', lltype.Ptr(lltype.GcStruct('y'))))
+    cpu.assembler._ovf_error_vtable = llmemory.cast_ptr_to_adr(lltype.nullptr(TP))
+    cpu.assembler._ovf_error_inst = cpu.assembler._ovf_error_vtable
     
     p0 = BoxPtr()
     p1 = BoxPtr()
@@ -283,5 +285,5 @@
 
     ops[-1].jump_target = ops[0]
     cpu.compile_operations(ops)
-    args = p0, p1, i2, i3, i4, i5, p6, p7, i8, i9, i10, i11, p12, p31
+    args = [p0, p1, i2, i3, i4, i5, p6, p7, i8, i9, i10, i11, p12, p13]
     res = cpu.execute_operations_in_new_frame('foo', ops, args)