[pypy-svn] r67114 - in pypy/branch/pyjitpl5/pypy/jit/backend/x86: . test

[arigo at codespeak.net]

Author: arigo
Date: Sun Aug 23 14:52:06 2009
New Revision: 67114

Modified:
   pypy/branch/pyjitpl5/pypy/jit/backend/x86/jump.py
   pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_jump.py
Log:
(benjamin, arigo)
Push and pop a random register if needed.


Modified: pypy/branch/pyjitpl5/pypy/jit/backend/x86/jump.py
==============================================================================
--- pypy/branch/pyjitpl5/pypy/jit/backend/x86/jump.py	(original)
+++ pypy/branch/pyjitpl5/pypy/jit/backend/x86/jump.py	Sun Aug 23 14:52:06 2009
@@ -1,16 +1,24 @@
-from pypy.jit.backend.x86.ri386 import MODRM
+from pypy.jit.backend.x86.ri386 import MODRM, eax
 
 
 def remap_stack_layout(assembler, src_locations, dst_locations, free_regs=[]):
+    pending_pops = []
     for i in range(len(dst_locations)):
         src = src_locations[i]
         dst = dst_locations[i]
         if src is not dst:
             if isinstance(dst, MODRM):
                 if isinstance(src, MODRM):
-                    tmp = free_regs[0]
+                    if free_regs:
+                        tmp = free_regs[0]
+                    else:
+                        assembler.regalloc_push(eax)
+                        pending_pops.append(eax)
+                        tmp = eax
                     assembler.regalloc_load(src, tmp)
                     src = tmp
                 assembler.regalloc_store(src, dst)
             else:
                 assembler.regalloc_load(src, dst)
+    for reg in pending_pops:
+        assembler.regalloc_pop(reg)

Modified: pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_jump.py
==============================================================================
--- pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_jump.py	(original)
+++ pypy/branch/pyjitpl5/pypy/jit/backend/x86/test/test_jump.py	Sun Aug 23 14:52:06 2009
@@ -11,6 +11,12 @@
     def regalloc_store(self, from_loc, to_loc):
         self.ops.append(('store', from_loc, to_loc))
 
+    def regalloc_push(self, loc):
+        self.ops.append(('push', loc))
+
+    def regalloc_pop(self, loc):
+        self.ops.append(('pop', loc))
+
 
 def test_trivial():
     assembler = MockAssembler()
@@ -44,3 +50,17 @@
                              ('store', edx, s20),
                              ('store', eax, s24),
                              ('load', s12, edi)]
+
+def test_simple_stacklocs_no_free_reg():
+    assembler = MockAssembler()
+    s8 = mem(ebp, -8)
+    s12 = mem(ebp, -12)
+    s20 = mem(ebp, -20)
+    s24 = mem(ebp, -24)
+    remap_stack_layout(assembler, [s8, ebx, s12], [s20, s24, edi], [])
+    assert assembler.ops == [('push', eax),
+                             ('load', s8, eax),
+                             ('store', eax, s20),
+                             ('store', ebx, s24),
+                             ('load', s12, edi),
+                             ('pop', eax)]