[pypy-svn] r58443 - pypy/branch/oo-jit/pypy/jit/codegen/x86_64
witulski at codespeak.net
witulski at codespeak.net
Fri Sep 26 13:40:46 CEST 2008
Author: witulski
Date: Fri Sep 26 13:40:46 2008
New Revision: 58443
Modified:
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py
Log:
Added shift left/right operations + Tests
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py Fri Sep 26 13:40:46 2008
@@ -189,6 +189,8 @@
_MOV_QWREG_QWREG = make_two_operand_instr( 1, None, 0, None, "\x89", 3, None, None)
_MOV_QWREG_IMM64 = make_two_operand_instr_with_alternate_encoding(1,0,0,None,"B8",None,None)
+ _IDIV_QWREG = make_one_operand_instr( 1, 0, 0, None, "\xF7", 3, None, 7)
+
_IMUL_QWREG_QWREG = make_two_operand_instr( 1, None, 0, None, "\x0F", 3, None, None, None, "\xAF")
_IMUL_QWREG_IMM32 = make_two_operand_instr( 1, None, 0, None, "\x69", 3, None, "sameReg")
@@ -214,6 +216,9 @@
_SETLE_8REG = make_one_operand_instr( 0, 0, 0, 0, "\x0F", 3, None, 0,14)
_SETNE_8REG = make_one_operand_instr( 0, 0, 0, 0, "\x0F", 3, None, 0,5)
+ _SHL_QWREG = make_one_operand_instr( 1, 0, 0, None, "\xD3", 3, None, 4)
+ _SHR_QWREG = make_one_operand_instr( 1, 0, 0, None, "\xD3", 3, None, 5)
+
_SUB_QWREG_QWREG = make_two_operand_instr( 1, None, 0, None, "\x28", 3, None, None)
_SUB_QWREG_IMM32 = make_two_operand_instr( 1, 0, 0, 0, "\x81", 3, None, 5)
@@ -272,6 +277,11 @@
method = getattr(self, "_MOV"+op1.to_string()+op2.to_string())
method(op1, op2)
+
+ def IDIV(self, op1):
+ method = getattr(self, "_IDIV"+op1.to_string())
+ method(op1)
+
def IMUL(self, op1, op2):
method = getattr(self, "_IMUL"+op1.to_string()+op2.to_string())
# exchange the two arguments because
@@ -300,6 +310,10 @@
method = getattr(self, "_SETL"+op1.to_string())
method(op1)
+ def SETR(self, op1):
+ method = getattr(self, "_SETR"+op1.to_string())
+ method(op1)
+
def SETGE(self, op1):
method = getattr(self, "_SETGE"+op1.to_string())
method(op1)
@@ -316,6 +330,14 @@
method = getattr(self, "_SETNE"+op1.to_string())
method(op1)
+ def SHL(self, op1):
+ method = getattr(self, "_SHL"+op1.to_string())
+ method(op1)
+
+ def SHR(self, op1):
+ method = getattr(self, "_SHR"+op1.to_string())
+ method(op1)
+
def SUB(self, op1, op2):
method = getattr(self, "_SUB"+op1.to_string()+op2.to_string())
method(op1, op2)
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py Fri Sep 26 13:40:46 2008
@@ -99,17 +99,42 @@
op_int_add = make_two_argument_method("ADD")
op_int_and = make_two_argument_method("AND")
- op_int_dec = make_one_argument_method("DEC")
+ op_int_dec = make_one_argument_method("DEC") #for debuging
op_int_inc = make_one_argument_method("INC") #for debuging
op_int_mul = make_two_argument_method("IMUL")
op_int_neg = make_one_argument_method("NEG")
op_int_not = make_one_argument_method("NOT")
op_int_or = make_two_argument_method("OR")
- op_int_push = make_one_argument_method("PUSH")
- op_int_pop = make_one_argument_method("POP")
+ op_int_push = make_one_argument_method("PUSH") #for debuging
+ op_int_pop = make_one_argument_method("POP") #for debuging
op_int_sub = make_two_argument_method("SUB")
op_int_xor = make_two_argument_method("XOR")
+ # FIXME: uses rcx insted of cl
+ def op_int_lshift(self, gv_x, gv_y):
+ gv_z = self.allocate_register("rcx")
+ #self.mc.XOR(gv_z, gv_z)
+ self.mc.MOV(gv_z, gv_y)
+ self.mc.SHL(gv_x)
+ return gv_x
+
+ # FIXME: uses rcx insted of cl
+ def op_int_rshift(self, gv_x, gv_y):
+ gv_z = self.allocate_register("rcx")
+ #self.mc.XOR(gv_z, gv_z)
+ self.mc.MOV(gv_z, gv_y)
+ self.mc.SHR(gv_x)
+ return gv_x
+
+ # IDIV RDX:RAX with QWREG
+ # FIXME: supports only RAX with QWREG
+ def op_int_div(self, gv_x, gv_y):
+ gv_z = self.allocate_register("rax")
+ self.mc.MOV(gv_z, gv_x)
+ self.mc.IDIV(gv_y)
+ return gv_y #FIXME: return gv_x?
+
+
#FIXME: can only jump 32bit
#FIXME: -6 displacement: the displ+ rip of next instr
def jump_if_true(self, gv_condition, args_for_jump_gv):
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