[pypy-svn] r58781 - in pypy/branch/oo-jit/pypy/jit/codegen/x86_64: . test
witulski at codespeak.net
witulski at codespeak.net
Tue Oct 7 18:13:49 CEST 2008
Author: witulski
Date: Tue Oct 7 18:13:47 2008
New Revision: 58781
Modified:
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py
Log:
fixed the alternate encoding bug (wrong opcodes where written to memory)
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py Tue Oct 7 18:13:47 2008
@@ -127,7 +127,7 @@
new_opcode = hex(int(opcode,16)+modrm1)
assert len(new_opcode[2:len(new_opcode)]) == 2
self.write_rex_byte(rexW, rexR, rexX, rexB)
- self.write(new_opcode[2:len(new_opcode)])
+ self.write(chr(int(new_opcode[2:len(new_opcode)],16)))
self.writeImm64(arg2.value)
return quadreg_instr
@@ -148,7 +148,7 @@
new_opcode = hex(int(opcode,16)+modrm1)
assert len(new_opcode[2:len(new_opcode)]) == 2
self.write_rex_byte(rexW, rexR, rexX, rexB)
- self.write(new_opcode[2:len(new_opcode)])
+ self.write(chr(int(new_opcode[2:len(new_opcode)],16)))
return quadreg_instr
class X86_64CodeBuilder(object):
@@ -221,6 +221,7 @@
_SUB_QWREG_QWREG = make_two_operand_instr( 1, None, 0, None, "\x29", 3, None, None)
_SUB_QWREG_IMM32 = make_two_operand_instr( 1, 0, 0, 0, "\x81", 3, None, 5)
+ _XOR_QWREG_IMM32 = make_two_operand_instr( 1, 0, 0, None, "\x81", 3, None, 6)
_XOR_QWREG_QWREG = make_two_operand_instr( 1, None, 0, None, "\x31", 3, None, None)
# TODO: maybe a problem with more ore less than two arg.
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py Tue Oct 7 18:13:47 2008
@@ -122,12 +122,16 @@
op_int_sub = make_two_argument_method("SUB")
op_int_xor = make_two_argument_method("XOR")
+ # TODO: support reg8
+ def op_cast_bool_to_int(self, gv_x):
+ assert isinstance(gv_x, Register64)
+ return gv_x
+
+ # 0 xor 1 == 1
+ # 1 xor 1 == 0
def op_bool_not(self, gv_x):
- gv_y = self.allocate_register()
- self.mc.MOV(gv_y, Immediate32(1))
- self.mc.XOR(gv_x, gv_y)
- return gv_x
-
+ self.mc.XOR(gv_x, Immediate32(1))
+ return gv_x
# FIXME: is that lshift val?
# FIXME: uses rcx insted of cl
@@ -151,7 +155,7 @@
gv_w = self.allocate_register("rdx")
self.mc.MOV(gv_z, gv_x)
self.mc.CDQ() #sign extention of rdx:rax
- if isinstance(gv_y, Immediate32):
+ if isinstance(gv_y, Immediate32): #support imm32
gv_u = self.allocate_register()
self.mc.MOV(gv_u,gv_y)
self.mc.IDIV(gv_u)
@@ -212,7 +216,7 @@
self.mc.SETGE(Register8("al"))
return Register64("rax")
- # moves to pass arg. when making a jump to a block
+ # the moves to pass arg. when making a jump to a block
def _compute_moves(self, outputargs_gv, targetargs_gv):
tar2src = {}
tar2loc = {}
@@ -337,8 +341,8 @@
builder = Builder()
# TODO: Builder._open()
entrypoint = builder.mc.tell()
- # TODO: support more than two reg
- register_list = ["rdi","rsi"]
+ # from http://www.x86-64.org/documentation/abi.pdf
+ register_list = ["rdi","rsi","rdx","rcx","r8","r9"]
# fill the list with the correct registers
inputargs_gv = [builder.allocate_register(register_list[i])
for i in range(len(arg_tokens))]
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py Tue Oct 7 18:13:47 2008
@@ -102,7 +102,7 @@
def make_one_op_imm_instr(rgenop, instr_name, num):
sigtoken = rgenop.sigToken(lltype.FuncType([lltype.Signed, lltype.Signed], lltype.Signed))
- builder, gv_op_imm, [gv_x, gv_y] = rgenop.newgraph(sigtoken, "mul")
+ builder, gv_op_imm, [gv_x, gv_y] = rgenop.newgraph(sigtoken, "one_op_imm_instr")
builder.start_writing()
gv_result = builder.genop2(instr_name, gv_x, rgenop.genconst(num))
builder.finish_and_return(sigtoken, gv_result)
@@ -166,12 +166,12 @@
# Illegal instruction at mov(qwreg,imm64)
- #def test_mul_im64(self):
- # rgenop = self.RGenOp()
- # mul_function = make_mul_imm(rgenop,int("123456789",16))
- # fnptr = self.cast(mul_function,1)
- # res = fnptr(2)
- # assert res == int("123456789",16)*2
+ def test_mul_imm64(self):
+ rgenop = self.RGenOp()
+ mul_function = make_one_op_imm_instr(rgenop, "int_mul", int("123456789",16))
+ fnptr = self.cast(mul_function,1)
+ res = fnptr(2)
+ assert res == int("123456789",16)*2
def test_imul(self):
mul_function = make_two_op_instr(self.RGenOp(), "int_mul")
@@ -467,7 +467,7 @@
test_calling_pause_direct = skip
test_longwinded_and_direct = skip
test_condition_result_cross_link_direct = skip
- test_multiple_cmps = skip##
+ test_multiple_cmps = skip
test_flipped_cmp_with_immediate = skip
test_jump_to_block_with_many_vars = skip
test_same_as = skip
@@ -475,7 +475,6 @@
test_like_residual_red_call_with_exc_direct = skip
test_call_functions_with_different_signatures_direct = skip
test_defaultonly_switch = skip
- ## test_bool_not_direct = skip
test_read_frame_var_direct = skip
test_read_frame_var_float_direct = skip
test_genconst_from_frame_var_direct = skip
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